LH28F160BGE-TTL10 Sharp Electronics, LH28F160BGE-TTL10 Datasheet
LH28F160BGE-TTL10
Specifications of LH28F160BGE-TTL10
Related parts for LH28F160BGE-TTL10
LH28F160BGE-TTL10 Summary of contents
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... Their enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F160BG-TL/BGH-TL offer two levels of protection : absolute protection with V selective hardware boot block locking. These alternatives give designers ultimate control of their code security needs ...
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PIN CONNECTIONS 60-BALL CSP 48-PIN TSOP (Type ...
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BLOCK ORGANIZATION This product features an asymmetrically-blocked architecture providing system memory integration. Each erase block can be erased independently of the others up to 100 000 times. For the address locations of the blocks, see the memory map in Fig. ...
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... SUPPLY PP word write with an invalid V spurious results and should not be attempted. DEVICE POWER SUPPLY : 2 not float any power pins. With all write attempts to the flash memory are inhibited. Device operations at invalid LKO V SUPPLY CC V voltage (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results CC and should not be attempted ...
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... V V suspend mode enables the system to read data off during read from, or write data to any other flash memory array PP location. The boot block is located at either the top or the bottom ...
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Status polling using RY/BY# minimizes both CPU overhead and system power consumption. When low, RY/BY# indicates that the WSM is performing a block erase ...
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Top Boot FFFFF 4 k-Word Boot Block FF000 FEFFF 4 k-Word Boot Block FE000 FDFFF 4 k-Word Parameter Block FD000 FCFFF 4 k-Word Parameter Block FC000 FBFFF 4 k-Word Parameter Block FB000 FAFFF 4 k-Word Parameter Block FA000 F9FFF 4 ...
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... BUS OPERATION The local CPU reads and writes flash memory in- system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Information can be read from any block, identifier codes or status register independent of the V voltage ...
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... Time t after RP# goes to logic-high (V IH command can be written. As with any automated device important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase word write modes ...
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The CUI does not occupy an addressable memory location written when WE# and CE# are active. The address and data needed to execute a command are latched on the rising edge of WE# or CE# (whichever goes high ...
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BUS CYCLES COMMAND REQ Read Array/Reset Read Identifier Codes Read Status Register Clear Status Register Block Erase Word Write Block Erase and Word Write Suspend Block Erase and Word Write Resume NOTES : 1. Bus operations are defined in Table ...
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Read Array Command Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until ...
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The CUI remains in read status register mode until a new command is issued. This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in ...
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... IH 4.9.1 V The V PP complete write protection of all blocks in the flash device. 4.9.2 WP The lockable blocks are locked when WP any program or erase operation to a locked block will result in an error, which will be reflected in the status register. For top configuration, the top two boot blocks are lockable ...
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Table 4 Write Protection Alternatives OPERATION V RP# WP All Blocks Locked All Blocks Locked. Block Erase All Blocks Unlocked > V PPLK V 2 Boot Blocks Locked. ...
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Start Write 20H, Block Address Write D0H, Block Address Read Status Register Suspend Block No Erase Loop 0 Suspend SR.7 = Block Erase Yes 1 Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register ...
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Start Write 40H or 10H, Address Write Word Data and Address Read Status Register Suspend Word No Write Loop 0 Suspend SR.7 = Word Write Yes 1 Full Status Check if Desired Word Write Complete FULL STATUS CHECK PROCEDURE Read ...
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Start Write B0H Read Status Register 0 SR Block Erase SR.6 = Completed 1 Read Read Word Write or Word Write? Read Array Data Word Write Loop No Done? Yes Write D0H Write FFH Block Erase Resumed ...
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Start Write B0H Read Status Register 0 SR Word Write SR.2 = Completed 1 Write FFH Read Array Data No Done Reading Yes Write D0H Write FFH Read Word Write Resumed Array Data Fig. 6 Word Write ...
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... GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductance. 5.4 V Trace on Printed Circuit Boards PP Updating flash memories that reside in the target system requires that the printed circuit board designers pay attention to the V trace. The V pin supplies the memory cell current PP for word writing and block erasing ...
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... When designing portable systems, designers must consider battery power consumption not only during or CE# PP device operation, but also for data retention during system idle time. Flash memory’s nonvolatility increases usable battery life because data is . LKO retained when system power is removed. ...
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ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings Operating Temperature • LH28F160BG-TL During Read, Block Erase and Word Write ............................ 0 to +70°C Temperature under Bias ............. –10 to +80°C • LH28F160BGH-TL During Read, Block Erase and Word Write ........................ –25 ...
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AC INPUT/OUTPUT TEST CONDITIONS 2.7 INPUT 0.0 AC test inputs are driven at 2.7 V for a logic "1" and 0.0 V for a Logic "0". Input timing begins, and output timing ends, at 1.35 V. Input rise and ...
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DC CHARACTERISTICS SYMBOL PARAMETER I Input Load Current LI I Output Leakage Current Standby Current CCS Deep Power-Down Current CCD Read Current CCR Word Write Current CCW ...
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DC CHARACTERISTICS (contd.) SYMBOL PARAMETER V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage (TTL) OH1 V Output High Voltage (CMOS) OH2 V Lockout Voltage during PP V PPLK ...
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AC CHARACTERISTICS - READ-ONLY OPERATIONS V = 2 +70 • VERSIONS SYMBOL PARAMETER t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV ...
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Standby V IH ADDRESSES ( CE# ( OE# ( WE# ( High Z DATA (D/Q) (DQ - ...
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AC CHARACTERISTICS FOR WE#-CONTROLLED WRITE OPERATIONS V = 2 +70 • VERSIONS SYMBOL PARAMETER t Write Cycle Time AVAV t RP# High Recovery to WE# Going Low PHWL t CE# ...
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V IH ADDRESSES ( CE# ( ELWL V IH OE# ( WE# ( High Z DATA (D/ PHWL ...
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AC CHARACTERISTICS FOR CE#-CONTROLLED WRITE OPERATIONS • 2 +70˚C or – VERSIONS SYMBOL PARAMETER t Write Cycle Time AVAV t RP# High Recovery to CE# Going ...
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V IH ADDRESSES ( WE# ( WLEL V IH OE# ( CE# ( High Z DATA (D/ PHEL IL ...
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RESET OPERATIONS High Z RY/BY# ( RP# ( High Z RY/BY# ( RP RP# ( Fig. ...
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BLOCK ERASE AND WORD WRITE PERFORMANCE • 2 +70°C or – SYMBOL PARAMETER t 32 k-Word Block WHQV1 Word Write Time t 4 k-Word Block EHQV1 ...
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... ORDERING INFORMATION Product line designator for all SHARP Flash products (H) E Device Density 160 = 16 M-bit Architecture B = Boot Block Power Supply Type G = Smart 3 Technology Operating Temperature Blank = –25 to +85 C OPTION ORDER CODE 1 LH28F160BGXX-XTL10 2 LH28F160BGXX-XTL12 LH28F160BG-TL/BGH- Access Speed (ns 100 ns (2 120 ns (2.7 to 3.6 V) Limited Voltage Option ...
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TSOP (TSOP048-P-1220 20.0 0.3 18.4 0.2 Package base plane 0.1 19.0 PACKAGING ...
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CSP (FBGA060/048-P-0811 0.1 S TYP. 1.1 TYP. 0.8 TYP. 0 TYP 0.2 11 0.03 0. ...