CY7B994V-2AI Cypress Semiconductor Corp, CY7B994V-2AI Datasheet

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CY7B994V-2AI

Manufacturer Part Number
CY7B994V-2AI
Description
Manufacturer
Cypress Semiconductor Corp
Type
Zero Delay PLL Clock Bufferr
Datasheet

Specifications of CY7B994V-2AI

Number Of Elements
1
Supply Current
250mA
Pll Input Freq (min)
24MHz
Pll Input Freq (max)
200MHz
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
-40C to 85C
Package Type
TQFP
Output Frequency Range
24 to 200MHz
Operating Supply Voltage (min)
2.97V
Operating Supply Voltage (max)
3.63V
Operating Temperature Classification
Industrial
Pin Count
100
Lead Free Status / Rohs Status
Not Compliant
Cypress Semiconductor Corporation
Document #: 38-07127 Rev. *F
Features
• 500-ps max. Total Timing Budget™ (TTB™) window
• 12–100-MHz (CY7B993V), or 24–200-MHz (CY7B994V)
• Matched pair output skew < 200 ps
• Zero input-to-output delay
• 18 LVTTL outputs driving 50Ω terminated lines
• 16 outputs at 200 MHz: Commercial temperature
• 6 outputs at 200 MHz: Industrial temperature
• 3.3V LVTTL/LVPECL, fault-tolerant, and hot insertable
• Phase adjustments in 625-/1300-ps steps up to ± 10.4 ns
• Multiply/divide ratios of 1–6, 8, 10, 12
• Individual output bank disable
• Output high-impedance option for testing purposes
• Fully integrated phase-locked loop (PLL) with lock
• <50-ps typical cycle-to-cycle jitter
• Single 3.3V ± 10% supply
• 100-pin TQFP package
• 100-lead BGA package
Functional
Block Diagram
input/output operation
reference inputs
indicator
Feedback Bank
Bank 2
REFSEL
Bank 4
Bank 3
Bank 1
REFA+
REFA–
REFB+
REFB–
FBSEL
FBKA+
FBKA–
FBKB+
FBKB–
High-speed Multi-phase PLL Clock Buffer
FBDS0
FBDS1
FBDIS
3DS0
3DS1
2DS0
2DS1
1DS0
1DS1
4DS0
4DS1
INV3
FBF0
DIS4
DIS3
DIS2
DIS1
3F0
3F1
2F0
2F1
1F0
1F1
4F0
4F1
3901 North First Street
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Phase
Freq.
Detector
OUTPUT_MODE
Divide and
Phase
Select
Matrix
Divide and
Phase
Select
Matrix
Divide and
Phase
Select
Matrix
Divide and
Phase
Select
Matrix
Divide and
Phase
Select
Matrix
Filter
FS
Functional Description
The CY7B993V and CY7B994V High-speed Multi-phase PLL
Clock Buffers offer user-selectable control over system clock
functions. This multiple-output clock driver provides the
system integrator with functions necessary to optimize the
timing of high-performance computer and communication
systems.
These devices feature a guaranteed maximum TTB window
specifying all occurrences of output clocks with respect to the
input reference clock across variations in output frequency,
supply voltage, operating temperature, input edge rate, and
process.
Eighteen configurable outputs each drive terminated trans-
mission lines with impedances as low as 50Ω while delivering
minimal and specified output skews at LVTTL levels. The outputs
are arranged in five banks. Banks 1 to 4 of four outputs allow
a divide function of 1 to 12, while simultaneously allowing
phase adjustments in 625–1300-ps increments up to 10.4 ns.
One of the output banks also includes an independent clock
invert function. The feedback bank consists of two outputs,
which allows divide-by functionality from 1 to 12 and limited
phase adjustments. Any one of these eighteen outputs can be
connected to the feedback input as well as driving other inputs.
Selectable reference input is a fault tolerance feature that
allows smooth change-over to secondary clock source, when
the primary clock source is not in operation. The reference
inputs and feedback inputs are configurable to accommodate
both LVTTL or Differential (LVPECL) inputs. The completely
integrated PLL reduces jitter and simplifies board layout.
3
3
VCO
2QA0
2QA1
3QA0
3QA1
3QB0
3QB1
2QB0
2QB1
1QA0
1QA1
4QA0
4QA1
1QB0
1QB1
QFA0
QFA1
4QB0
4QB1
San Jose
Control Logic
Divide and Phase
Generator
,
CA 95134
LOCK
Revised August 10, 2005
RoboClock
CY7B993V
CY7B994V
408-943-2600
[+] Feedback

Related parts for CY7B994V-2AI

CY7B994V-2AI Summary of contents

Page 1

... Cypress Semiconductor Corporation Document #: 38-07127 Rev. *F High-speed Multi-phase PLL Clock Buffer Functional Description The CY7B993V and CY7B994V High-speed Multi-phase PLL Clock Buffers offer user-selectable control over system clock functions. This multiple-output clock driver provides the system integrator with functions necessary to optimize the timing of high-performance computer and communication systems ...

Page 2

... VCCQ 20 4DS0 21 3DS0 22 2DS0 23 1DS0 24 GND Document #: 38-07127 Rev. *F 100-pin TQFP CY7B993/  RoboClock CY7B993V CY7B994V VCCQ 74 REFA+ 73 REFA – 72 REFSEL 71 REFB– 70 REFB+ 69 2F0 GND 66 2QA0 65 VCCN 64 2QA1 63 GND 62 GND 61 2QB0 60 VCCN 59 2QB1 58 GND 57 FBF0 56 1F0 55 GND 54 VCCQ ...

Page 3

... VCCN VCCN GND (3_level) VCCN 3QA0 3QA1 GND 3QB0 Pin Description , LOW indicates a connection to GND, and MID indicates an open connection. Internal termination CC  RoboClock CY7B993V CY7B994V 9 10 FBKA– FBKA+ FBSEL REFA+ GND REFA– VCCN REFB+ VCCN 2QA0 1F0 2QA1 ...

Page 4

... NOM There are two versions: a low-speed device (CY7B993V) where f ranges from 12 MHz to 100 MHz, and a NOM high-speed device (CY7B994V) that ranges from 24 MHz to 200 MHz. The FS setting for each device is shown in Table 1. The f frequency is seen on “divide-by-one” outputs. For NOM the CY7B994V, the upper f ...

Page 5

... REF. For example, if the output used for feedback is programmed to shift –8t forward in time skew will effectively be skewed 16t ) of the V and Phase Generator. f NOM CO when the output connected undivided. NOM  RoboClock CY7B993V CY7B994V Output Skew Function Feed- back Bank1 Bank2 Bank3 Bank4 Bank –4t –4t –8t –8t – ...

Page 6

... When a bank of outputs is disabled to HI-Z state, the respective bank of outputs will go HI-Z immediately. Table 5. DIS[1:4]/FBDIS Pin Functionality OUTPUT_MODE DIS[1:4]/FBDIS HIGH/LOW LOW HIGH HIGH LOW HIGH MID X  CY7B993V CY7B994V Output Mode ENABLED HI-Z HOLD-OFF FACTORY TEST Page [+] Feedback ...

Page 7

... MHz is 16 (with 25-pF load and 0-m/s air flow). Typical Safe Operating Zone (25-pF Load, 0-m /s air flow ) 100 Safe Operating Zone Num ber of Outputs at 185 MHz Figure 2. Typical Safe Operating Zone  CY7B993V CY7B994V 16 18 Page [+] Feedback ...

Page 8

... Min mA Min. < Min. < GND Max Max Min. < Min. < Min. < GND IN RoboClock CY7B993V CY7B994V Ambient Temperature V CC ° ° 3.3V ± 10 +70 C ° ° 3.3V ± 10% – +85 C Min. Max. Unit = –30 mA 2.4 – Min. 2.4 – – 0 Min. – 0 µA – ...

Page 9

... Bank1 and FB Bank configured to run at maximum frequency (f CCI CY7B994V), and all other clock output banks to run at half the maximum frequency. FS and OUTPUT_MODE are asserted to the HIGH state. 8. This is dependent upon frequency and number of outputs of a bank being loaded. The value indicates maximum I load terminated to 50Ω ...

Page 10

... OUTPUT 200 MHz (a) LVTTL AC Test Load 3.3V 2.0V 0.8V GND < (b) TTL Input Test Waveform = 185 MHz 200 MHz. L RoboClock CY7B993V CY7B994V CY7B993/4V-5 Typ. Max. Min. Typ. Max. Unit – 500 – – 700 ps – 200 – – ...

Page 11

... CY7B993V-2AI 250 100 CY7B993V-2AIT 250 200 CY7B994V-2AC 250 200 CY7B994V-2ACT 250 200 CY7B994V-2BBC 250 200 CY7B994V-2BBCT 250 200 CY7B994V-2AI 250 200 CY7B994V-2AIT 250 200 CY7B994V-2BBI 250 200 CY7B994V-2BBIT Document #: 38-07127 Rev. *F QFA0 or [1:4]Q[A:B]0 t SKEWPR t PWL QFA1 or [1:4]Q[A:B]1 0.8V t [1:4]QA[0:1] CCJ1-3,4-12 t SKEWBNK ...

Page 12

... CY7B993V-2AXI 250 100 CY7B993V-2AXIT 250 200 CY7B994V-2AXC 250 200 CY7B994V-2AXCT 250 200 CY7B994V-2BBXC 250 200 CY7B994V-2BBXCT 100-ball Thin Ball Grid Array - Tape and Reel 250 200 CY7B994V-2AXI 250 200 CY7B994V-2AXIT 250 200 CY7B994V-2BBXI 250 200 CY7B994V-2BBXIT 500 100 CY7B993V-5AXC 500 ...

Page 13

... Package Diagrams 100-pin Thin Plastic Quad Flat Pack (TQFP) A100 Document #: 38-07127 Rev. *F  RoboClock CY7B993V CY7B994V 51-85048-*B Page [+] Feedback ...

Page 14

... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  RoboClock CY7B993V CY7B994V 51-85107-*B Page [+] Feedback ...

Page 15

... Added three industrial packages HWT Added TTB Features RBI Power-up requirements to operating conditions information RGL Added min. F value of 12 MHz for CY7B993V and 24 MHz for CY7B994V out to switching characteristics table Corrected prop delay limit parameter from (t Output Description paragraph RGL Added clock input frequency (f ...

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