CY7C09199-6AC Cypress Semiconductor Corp, CY7C09199-6AC Datasheet

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CY7C09199-6AC

Manufacturer Part Number
CY7C09199-6AC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C09199-6AC

Density
1.125Mb
Access Time (max)
15ns
Sync/async
Synchronous
Architecture
SDR
Clock Freq (max)
52MHz
Operating Supply Voltage (typ)
5V
Address Bus
17b
Package Type
TQFP
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
450mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Word Size
9b
Number Of Words
128K
Lead Free Status / Rohs Status
Not Compliant
25/0251
Cypress Semiconductor Corporation
Document #: 38-06039 Rev. *A
Features
Notes:
1.
2.
3.
• True dual-ported memory cells which allow simulta-
• Six Flow-Through/Pipelined devices
• Three Modes
• Pipelined output mode on both ports allows fast 100-
• 0.35-micron CMOS for optimum speed/power
• High-speed clock to data access 6.5
Logic Block Diagram
R/W
OE
CE
CE
FT/Pipe
I/O
A
CLK
ADS
CNTEN
CNTRST
neous access of the same memory location
MHz cycle time
(max.)
— 64K x 8/9 organizations (CY7C09089/189)
— 128K x 8/9 organizations (CY7C09099/199)
— Flow-Through
— Pipelined
— Burst
0
See page 7 for Load Conditions.
I/O
A
–A
0L
0L
1L
0
L
–A
0
L
L
L
–I/O
–I/O
[3]
15/16L
15
L
L
for 64K; and A
7
[2]
L
7/8L
for x8 devices; I/O
16/17
0
–A
For the most recent information, visit the Cypress web site at www.cypress.com
16
0
for 128K devices.
–I/O
8/9
0/1
0/1
1
0
1
Counter/
Address
Register
8
Decode
for x9 devices.
0
[1]
/7.5/9/12 ns
3901 North First Street
Control
I/O
True Dual-Ported
Synchronous Dual-Port Static RAM
RAM Array
• Low operating power
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
• Dual Chip Enables for easy depth expansion
• Automatic power-down
• Commercial and Industrial temperature ranges
• Available in 100-pin TQFP
• Pin-compatible and functionally equivalent to IDT70908
and IDT709089
— Active = 195 mA (typical)
— Standby = 0.05 mA (typical)
— Shorten cycle times
— Minimize bus noise
— Supported in Flow-Through and Pipelined modes
Control
I/O
San Jose
0
Counter/
Register
Address
Decode
CA 95134
0/1
1
1
0
0/1
64K/128K x 8/9
8/9
Revised December 27, 2002
CY7C09089/99
CY7C09189/99
16/17
I/O
408-943-2600
A
0R
CNTRST
0
FT/Pipe
CNTEN
–A
–I/O
ADS
[3]
15/16R
R/W
CLK
CE
CE
OE
[2]
7/8R
0R
1R
R
R
R
R
R
R
R
[+] Feedback

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CY7C09199-6AC Summary of contents

Page 1

... For the most recent information, visit the Cypress web site at www.cypress.com Cypress Semiconductor Corporation Document #: 38-06039 Rev. *A Synchronous Dual-Port Static RAM • Low operating power — Active = 195 mA (typical) — Standby = 0.05 mA (typical) • Fully synchronous interface for easier operation • ...

Page 2

Functional Description The CY7C09089/99 and CY7C09189/99 are high-speed syn- chronous CMOS 64K and 128K x 8/9 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. isters on control, address, ...

Page 3

Pin Configurations 100 A7L 3 A8L 4 A9L 5 A10L 6 A11L 7 A12L 8 A13L 9 A14L 10 A15L 11 [5] A16L 12 VCC ...

Page 4

... SB1 (Both ports TTL Level) Typical Standby Current for I (mA) SB3 (Both ports CMOS Level) Note: 7. This pin is NC for CY7C09189. Document #: 38-06039 Rev. *A 100-Pin TQFP (Top View CY7C09199 (128K x 9) CY7C09189 (64K CY7C09089/99 CY7C09089/99 CY7C09189/99 CY7C09189/99 [ 100 83 6.5 7.5 ...

Page 5

... Outputs in High Z State ................................. –0.5V to +7.0V DC Input Voltage............................................ –0.5V to +7.0V Note: 8. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 9. Industrial parts are available in CY7C09099 and CY7C09199 only. Document #: 38-06039 Rev. *A Description A for 64K; and A A for 128K devices). ...

Page 6

Electrical Characteristics Over the Operating Range Parameter Description V Output HIGH Voltage Min –4.0 mA Output LOW Voltage Min +4.0 mA Input HIGH Voltage ...

Page 7

AC Test Loads 893 OUTPUT 347 (a) Normal Load (Load 1) AC Test Loads (Applicable to -6 only OUTPUT 1.4V TH ...

Page 8

Switching Characteristics Over the Operating Range Parameter Description f f Flow-Through MAX1 Max f f Pipelined MAX2 Max t Clock Cycle Time - Flow-Through CYC1 t Clock Cycle Time - Pipelined CYC2 t Clock HIGH Time - Flow-Through CH1 t ...

Page 9

Switching Waveforms Read Cycle for Flow-Through Output (FT/PIPE = V t CYC1 t CH1 CLK R ADDRESS t CD1 DATA OUT t ...

Page 10

Switching Waveforms (continued) [18, 19] Bank Select Pipelined Read t CYC2 t t CH2 CL2 CLK ADDRESS A (B1 0(B1) DATA OUT(B1 ADDRESS A (B2) ...

Page 11

Switching Waveforms (continued) Pipelined Read-to-Write-to-Read ( CYC2 t t CH2 CL2 CLK R ADDRESS DATA IN DATA OUT ...

Page 12

Switching Waveforms (continued) Flow-Through Read-to-Write-to-Read ( CYC1 t t CH1 CL1 CLK R ADDRESS DATA IN t CD1 ...

Page 13

Switching Waveforms (continued) Pipelined Read with Address Counter Advance t CYC2 t t CH2 CL2 CLK ADDRESS SAD HAD ADS CNTEN t t SCN HCN DATA OUT ...

Page 14

Switching Waveforms (continued) Write with Address Counter Advance (Flow-Through or Pipelined Outputs) t CYC2 t t CH2 CL2 CLK ADDRESS n INTERNAL A n ADDRESS t t SAD HAD ADS CNTEN t t SCN HCN ...

Page 15

Switching Waveforms (continued) [17, 24, 30, 31] Counter Reset (Pipelined Outputs) t CYC2 t t CH2 CL2 CLK ADDRESS INTERNAL A X ADDRESS SAD HAD ADS t t SCN HCN CNTEN t t SRST HRST ...

Page 16

Read/Write and Enable Operation Inputs OE CLK Address Counter Control Operation Previous Address Address CLK ADS CNTEN ...

Page 17

... Ordering Code 6.5 CY7C09189-6AC 7.5 CY7C09189-7AC 9 CY7C09189-9AC 12 CY7C09189-12AC 128K x9 Synchronous Dual-Port SRAM Speed (ns) Ordering Code 6.5 CY7C09199-6AC 7.5 CY7C09199-7AC 9 CY7C09199-9AC CY7C09199-9AI 12 CY7C09199-12AC Document #: 38-06039 Rev. *A Package Name Package Type A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack ...

Page 18

... Document #: 38-06039 Rev. *A © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...

Page 19

Document Title: CY7C09089/99, CY7C09189/99 64K/128K x 8/9 Synchronous Dual Port Static RAM Document Number: 38-06039 Issue REV. ECN NO. Date Change ** 110187 10/21/01 *A 122289 12/27/02 Document #: 38-06039 Rev. *A Orig. of Description of Change SZV Change from ...

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