CY7C09199-9AI Cypress Semiconductor Corp, CY7C09199-9AI Datasheet - Page 2

• Manufacturer Part Number: CY7C09199-9AI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09199-9AI

• Density: 1.125Mb
• Access Time (max): 9ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 40MHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 17b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Number Of Ports: 2
• Supply Current: 410mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 9b
• Number Of Words: 128K
• Lead Free Status / Rohs Status: Not Compliant

Functional Description
The CY7C09089/99 and CY7C09189/99 are high-speed syn-
chronous CMOS 64K and 128K x 8/9 dual-port static RAMs.
Two ports are provided, permitting independent, simultaneous
access for reads and writes to any location in memory.
isters on control, address, and data lines allow for minimal set-
up and hold times. In pipelined output mode, data is registered
for decreased cycle time. Clock to data valid t
(pipelined). Flow-through mode can also be used to bypass
the pipelined output register to eliminate access latency. In
flow-through mode data will be available t
address is clocked into the device. Pipelined output or flow-
through mode is selected via the FT/Pipe pin.
Each port contains a burst counter on the input address regis-
ter. The internal write pulse width is independent of the LOW-
to-HIGH transition of the clock signal. The internal write pulse
is self-timed to allow the shortest possible cycle times.
Note:
Document #: 38-06039 Rev. *A
4.
When writing simultaneously to the same location, the final value cannot be guaranteed.
CD1
= 15 ns after the
CD2
= 6.5 ns
[4]
Reg-
[1]
A HIGH on CE
down the internal circuitry to reduce the static power consump-
tion. The use of multiple Chip Enables allows easier banking
of multiple chips for depth expansion configurations. In the
pipelined mode, one cycle is required with CE
HIGH to reactivate the outputs.
Counter enable inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted,
the address counter will increment on each LOW-to-HIGH
transition of that port’s clock signal. This will read/write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array and will loop back to the start. Counter Reset (CNTRST)
is used to reset the burst counter.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
0
or LOW on CE
1
for one clock cycle will power
CY7C09089/99
CY7C09189/99
0
LOW and CE
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