CY7C09289-6AC Cypress Semiconductor Corp, CY7C09289-6AC Datasheet

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CY7C09289-6AC

Manufacturer Part Number
CY7C09289-6AC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C09289-6AC

Density
1Mb
Access Time (max)
15ns
Sync/async
Synchronous
Architecture
SDR
Clock Freq (max)
53MHz
Operating Supply Voltage (typ)
5V
Address Bus
16b
Package Type
TQFP
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
450mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Word Size
16b
Number Of Words
64K
Lead Free Status / Rohs Status
Not Compliant
25/0251
Cypress Semiconductor Corporation
Document #: 38-06040 Rev. *A
Features
Notes:
Logic Block Diagram
1.
2.
3.
4.
• True dual-ported memory cells which allow simulta-
• Six Flow-Through/Pipelined devices
• Three Modes
• Pipelined output mode on both ports allows fast 100-
• 0.35-micron CMOS for optimum speed/power
• High-speed clock to data access 6.5
R/W
UB
CE
CE
LB
OE
FT/Pipe
I/O
I/O
A
CLK
ADS
CNTEN
CNTRST
neous access of the same memory location
MHz cycle time
— 32K x 16/18 organization (CY7C09279/379)
— 64K x 16/18 organization (CY7C09289/389)
— Flow-Through
— Pipelined
— Burst
0L
See page 6 for Load Conditions.
I/O
I/O
A
L
8/9L
0L
L
0L
1L
0
L
–A
–A
8
0
L
L
L
–I/O
–I/O
–I/O
14
14/15L
–I/O
[4]
L
L
for 32K; A
15
7
L
7/8L
for x16 devices. I/O
[2]
[3]
for x16 devices; I/O
15/17L
0
15/16
–A
15
for 64K devices.
For the most recent information, visit the Cypress web site at www.cypress.com
8/9
8/9
0
9
–I/O
0/1
–I/O
0/1
1
0
1b
Counter/
Register
Address
Decode
8
17
b
for x18 devices.
0b 1a 0a
for x18 devices.
a
[1]
/7.5/9/12 ns (max.)
3901 North First Street
Control
I/O
True Dual-Ported
Synchronous Dual Port Static RAM
RAM Array
• Low operating power
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
• Dual Chip Enables for easy depth expansion
• Upper and Lower Byte Controls for Bus Matching
• Automatic power-down
• Commercial and Industrial temperature ranges
• Available in 100-pin TQFP
• Pin-compatible and functionally equivalent to IDT70927
and IDT709279
— Active = 195 mA (typical)
— Standby = 0.05 mA (typical)
— Shorten cycle times
— Minimize bus noise
— Supported in Flow-Through and Pipelined modes
Control
I/O
San Jose
0a
a
1a
Counter/
Register
Address
Decode
0b
b
CA 95134
1b
0/1
32K/64K x16/18
1
0
0/1
Revised December 27, 2002
CY7C09279/89
CY7C09379/89
8/9
8/9
15/16
I/O
8/9R
408-943-2600
I/O
A
0R
0R
CNTRST
–I/O
FT/Pipe
CNTEN
–A
–I/O
ADS
15/17R
[4]
14/15R
R/W
CLK
CE
CE
OE
UB
LB
[2]
[3]
7/8R
0R
1R
R
R
R
R
R
R
R
R
R
[+] Feedback

Related parts for CY7C09289-6AC

CY7C09289-6AC Summary of contents

Page 1

... Features • True dual-ported memory cells which allow simulta- neous access of the same memory location • Six Flow-Through/Pipelined devices — 32K x 16/18 organization (CY7C09279/379) — 64K x 16/18 organization (CY7C09289/389) • Three Modes — Flow-Through — Pipelined — Burst • Pipelined output mode on both ports allows fast 100- MHz cycle time • ...

Page 2

... Counter Reset (CNTRST) is used to reset the burst counter. All parts are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages. 100-Pin TQFP (Top View CY7C09289 (64K x 16) CY7C09279 (32K x 16 CY7C09279/89 CY7C09379/89 or LOW on CE for one clock cycle will power ...

Page 3

Pin Configurations (continued) 100 A9L 1 A10L 2 A11L 3 A12L 4 A13L 5 A14L 6 [8] 7 A15L LBL 8 UBL 9 CE0L 10 CE1L 11 CNTRSTL 12 R/WL 13 OEL 14 VCC 15 FT/PIPEL ...

Page 4

... DC Voltage Applied to Outputs in High Z State.................................. –0.5V to +7.0V DC Input Voltage............................................ –0.5V to +7.0V Note: 9. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 10. Industrial parts are available in CY7C09289 and Cy7C09389 only Document #: 38-06040 Rev. *A Description –A for 32K, A –A for 64K devices) ...

Page 5

Electrical Characteristics Over the Operating Range Parameter Description V Output HIGH Voltage Min –4.0 mA Output LOW Voltage Min +4.0 mA Input HIGH Voltage ...

Page 6

AC Test Loads 893 OUTPUT 347 (a) Normal Load (Load 1) AC Test Loads (Applicable to -6 only OUTPUT 1.4V TH ...

Page 7

Switching Characteristics Over the Operating Range Parameter Description f f Flow-Through MAX1 Max f f Pipelined MAX2 Max t Clock Cycle Time - Flow-Through CYC1 t Clock Cycle Time - Pipelined CYC2 t Clock HIGH Time - Flow-Through CH1 t ...

Page 8

Switching Waveforms Read Cycle for Flow-Through Output (FT/PIPE = V t CYC1 t CH1 CLK R ADDRESS t CD1 DATA OUT t ...

Page 9

Switching Waveforms (continued) [19, 20] Bank Select Pipelined Read t CYC2 t t CH2 CL2 CLK ADDRESS A (B1 0(B1) DATA OUT(B1 ADDRESS A (B2) ...

Page 10

Switching Waveforms (continued) Pipelined Read-to-Write-to-Read ( CYC2 t t CH2 CL2 CLK R ADDRESS DATA IN DATA OUT ...

Page 11

Switching Waveforms (continued) Flow-Through Read-to-Write-to-Read ( CYC1 t t CH1 CL1 CLK R ADDRESS DATA IN t CD1 ...

Page 12

Switching Waveforms (continued) Pipelined Read with Address Counter Advance t CYC2 t t CH2 CL2 CLK ADDRESS SAD HAD ADS CNTEN t t SCN HCN DATA OUT ...

Page 13

Switching Waveforms (continued) Write with Address Counter Advance (Flow-Through or Pipelined Outputs) t CYC2 t t CH2 CL2 CLK ADDRESS n INTERNAL A n ADDRESS t t SAD HAD ADS CNTEN t t SCN HCN ...

Page 14

Switching Waveforms (continued) [18, 30, 31, 32] Counter Reset (Pipelined Outputs) t CYC2 t t CH2 CL2 CLK ADDRESS INTERNAL A X ADDRESS SAD HAD ADS t t SCN HCN CNTEN t t SRST HRST ...

Page 15

Read/Write and Enable Operation Inputs OE CLK Address Counter Control Operation Previous Address Address CLK ADS CNTEN ...

Page 16

... Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 6.5 CY7C09279-6AC 7.5 CY7C09279-7AC 9 CY7C09279-9AC 12 CY7C09279-12AC 64K x16 Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 6.5 CY7C09289-6AC 7.5 CY7C09289-7AC 9 CY7C09289-9AC CY7C09289-9AI 12 CY7C09289-12AC 32K x18 Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 6.5 CY7C09379-6AC 7.5 CY7C09379-7AC 9 CY7C09379-9AC ...

Page 17

... Document #: 38-06040 Rev. *A © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...

Page 18

Document Title: CY7C09279/89, CY7C09379/89 32K/64K X 16/18 Synchronous Dual Port Static RAM Document Number: 38-06040 Issue Orig. of REV. ECN NO. Date Change ** 110188 09/29/01 SZV *A 122290 12/27/02 RBI Document #: 38-06040 Rev. *A Description of Change Change ...

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