CY7C1061AV33-10ZC Cypress Semiconductor Corp, CY7C1061AV33-10ZC Datasheet - Page 4

• Manufacturer Part Number: CY7C1061AV33-10ZC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1061AV33-10ZC

• Density: 16Mb
• Access Time (max): 10ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 20b
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 275mA
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 54
• Word Size: 16b
• Number Of Words: 1M
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05256 Rev. *F
AC Switching Characteristics
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
Notes:
10. These parameters are guaranteed by design and are not tested.
11. The internal Write time of the memory is defined by the overlap of CE
12. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
power
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
DBE
LZBE
HZBE
WC
SCE
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
BW
6. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
8. This part has a voltage regulator which steps down the voltage from 3V to 2V internally. t
9. t
minimum operating V
I
started.
voltage.
be LOW to initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the
leading edge of the signal that terminates the Write.
OL
HZOE
/I
Parameter
OH
, t
HZCE
and specified transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise.
, t
[11, 12]
HZWE
, t
HZBE
DD
, normal SRAM operation can begin including reduction in V
and t
V
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z
CE
CE
CE
CE
Byte Enable to Data Valid
Byte Enable to Low-Z
Byte Disable to High-Z
Write Cycle Time
CE
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z
WE LOW to High-Z
Byte Enable to End of Write
CC
LZOE
1
1
1
1
1
1
(typical) to the first access
LOW/CE
LOW/CE
HIGH/CE
LOW/CE
HIGH/CE
LOW/CE
, t
LZCE
, t
\LZWE
2
2
2
2
2
2
HIGH to Data Valid
HIGH to Low-Z
HIGH to Power-Up
HIGH to Write End
, t
Over the Operating Range
LOW to High-Z
LOW to Power-Down
LZBE
Description
[9]
[9]
[9]
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV from steady-state
[8]
[9]
[9]
1
[10]
LOW (CE
[10]
2
[7]
HIGH) and WE LOW. Chip enables must be active and WE and byte enables must
DD
to the data retention (V
power
HZWE
time has to be provided initially before a Read/Write operation is
Min.
5.5
10
10
1
3
1
3
0
1
7
7
0
0
7
0
3
7
and t
–10
DD
SD
(3.0V). As soon as 1ms (T
.
Max.
10
10
10
5
5
5
5
5
5
CCDR
, 2.0V) voltage.
Min.
12
12
1
3
1
3
0
1
8
8
0
0
8
6
0
3
8
CY7C1061AV33
–12
power
Max.
12
12
12
) after reaching the
6
6
6
6
6
6
Page 4 of 11
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns