CY7C1069AV33-12ZC Cypress Semiconductor Corp, CY7C1069AV33-12ZC Datasheet
CY7C1069AV33-12ZC
Specifications of CY7C1069AV33-12ZC
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CY7C1069AV33-12ZC Summary of contents
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... The input/output pins (I/O impedance state when the device is deselected (CE features CE LOW), the outputs are disabled (OE HIGH), or during Write operation (CE The CY7C1069AV33 is available in a 54-pin TSOP II package with center power and ground (revolutionary) pinout and a 60-ball fine-pitch ball grid array (FBGA) package. Data in Drivers ...
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... NC pins are not connected on the die. 2. DNU pins have to be left floating or tied to VSS to ensure proper application. Document #: 38-05255 Rev. *G –10 10 275 50 [1, 2] Figure 1. 54-Pin TSOP II Top View I/O I I/O I DNU I/O I I/O I CY7C1069AV33 –12 Unit 12 ns 260 Page 2 [+] Feedback ...
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... Pin Configuration Document #: 38-05255 Rev. *G [1, 2] Figure 2. 54-Pin TSOP II (Top View CE2 CE1 I I/O 4 I I/O 2 I DNU CY7C1069AV33 Page 3 [+] Feedback ...
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... IL MAX < 0.3V, Max > V – 0.3V > V – 0.3V, CC < 0.3V Test Conditions T = 25° MHz 3. CY7C1069AV33 [3] ................................ –0. 0.5V CC Ambient V CC Temperature 3.3V ± 0.3V 0°C to +70°C –40°C to +85°C –10 –12 Unit Max Min Max 2.4 V 0.4 0.4 ...
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... DD time has to be provided initially before a Read/Write operation power are specified with a load capacitance ( Test Loads. Transition is measured ±200 mV , and WE LOW LOW/CE HIGH 1 2 and t HZWE CY7C1069AV33 [5] R1 317 Ω 3.3V OUTPUT R2 5 pF* 351Ω *Including jig and scope (b) 10% Fall time: > ...
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... Data Hold from Write End HIGH to Low-Z LZWE t WE LOW to High-Z HZWE Document #: 38-05255 Rev. *G [7] Over the Operating Range (continued) –10 Min 7 5 Figure 4. Data Retention Waveform DATA RETENTION MODE 3.0V V > CDR CY7C1069AV33 –12 Unit Max Min Max 3. Page 6 [+] Feedback ...
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... Notes 13. Device is continuously selected 14 HIGH for Read cycle. 15. Address valid prior to or coincident with CE transition LOW and CE 1 Document #: 38-05255 Rev. *G [13, 14] Figure 5. Read Cycle No OHA t RC DATA VALID 50 transition HIGH. 2 CY7C1069AV33 DATA VALID [14, 15] t HZOE t HZSCE HIGH IMPEDANCE 50 Page 7 [+] Feedback ...
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... Document #: 38-05255 Rev. *G [16, 17, 18] Controlled SCE PWE SCE PWE t t HZWE SD –I/O Mode 0 7 Power Down Power Down Read All Bits Write All Bits Selected, Outputs Disabled . It is active low. 2 CY7C1069AV33 [16, 17, 18 LZWE Power Standby ( Standby ( Active ( Active ( Active ( Page 8 [+] Feedback ...
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... Ordering Information Speed (ns) Ordering Code 10 CY7C1069AV33-10ZC CY7C1069AV33-10ZXC CY7C1069AV33-10BAC CY7C1069AV33-10ZXI CY7C1069AV33-10BAI 12 CY7C1069AV33-12ZC CY7C1069AV33-12ZXC CY7C1069AV33-12ZI Package Diagrams Document #: 38-05255 Rev. *G Package Package Type Diagram 51-85160 54-pin TSOP II 54-pin TSOP II (Pb-free) 51-85162 60-ball ( 1.2 mm) FBGA 54-pin TSOP II (Pb-free) 51-85162 60-ball ( 1.2 mm) FBGA 51-85160 54-pin TSOP II ...
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... Document #: 38-05255 Rev. *G BOTTOM VIEW A1 CORNER DUMMY BALL (0.3) X12 Ø0. Ø0. Ø0.30±0.05(48X 1.875 A 0.75 0.75 1.00 3.75 6.00 B 8.00±0.10 0.15(4X) CY7C1069AV33 DIMENSIONS IN MM PART # STANDARD PKG. BA60A LEAD FREE PKG. BK60A PKG WEIGHT: 0.30 gms 51-85162-*D Page 10 [+] Feedback ...
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... Document History Page Document Title: CY7C1069AV33 Static RAM Document Number: 38-05255 Submission REV. ECN NO. Date ** 113724 03/27/02 *A 117060 07/31/02 *B 117990 08/30/02 *C 120385 11/13/02 *D 124441 2/25/03 *E 403984 See ECN *F 492137 See ECN *G 2784946 10/12/2009 Document #: 38-05255 Rev. *G Orig. of Description of Change Change NSL ...
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... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05255 Rev. *G All products and company names mentioned in this document may be the trademarks of their respective holders. psoc.cypress.com clocks.cypress.com image.cypress.com Revised October 12, 2009 CY7C1069AV33 Page 12 [+] Feedback ...