CY7C144-15AI Cypress Semiconductor Corp, CY7C144-15AI Datasheet
CY7C144-15AI
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CY7C144-15AI Summary of contents
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... Document #: 38-06034 Rev 8/9 Dual-Port Static RAM Functional Description The CY7C144 and CY7C145 are high speed CMOS and dual-port static RAMs. Various arbitration schemes are included on the CY7C144/5 to handle situations when multiple processors access the same piece of data. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory ...
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... Document #: 38-06034 Rev. *E Figure 2. 64-Pin TQFP (Top View GND 5 INT BUSY GND M/S 51 GND 9 BUSY INT Figure 3. 80-Pin TQFP (Top View CY7C145 CY7C144, CY7C145 INT L BUSY 42 GND CY7C144 41 M BUSY 38 INT INT 53 L BUSY 52 L GND 51 M/S 50 BUSY 49 R INT Page [+] Feedback ...
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... Ground Document #: 38-06034 Rev. *E 7C144-15 7C144-25 7C144-35 7C145-15 7C145-25 7C145- 220 180 60 40 Description is set when right port writes location 1FFE and is cleared when left port reads location L CY7C144, CY7C145 7C144-55 Unit 7C145- 160 160 pin is used when writing 0 Page [+] Feedback ...
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... Architecture The CY7C144/5 consists array of 8K words of 8/9 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes or reads to the same location, a BUSY pin is provided on each port ...
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... No port accessing semaphore address 1 0 Right port obtains semaphore port accessing semaphore 0 1 Left port obtains semaphore port accessing semaphore CY7C144, CY7C145 Operation Power Down Read Data in Semaphore I/O Lines Disabled Write to Semaphore Read Write Illegal Condition Right Port R INT 0− ...
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... V < 0.2V One Port Commercial > V – 0.2V Industrial V > V – 0. < 0.2V, Active IN [7] Port Outputs MAX CY7C144, CY7C145 Ambient Temperature V CC ° ° 5V ± 10 +70 C ° ° −40 5V ± 10 +85 C 7C144-15 7C144-25 7C145-15 7C145-25 Unit Min Max Min Max 2 ...
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... Figure 4. AC Test Loads and Waveforms R = 250Ω TH OUTPUT C = 30pF V = 1.4V TH (b) Th évenin Equivalent (Load 1) ALL INPUT PULSES 3.0V 90% 90% 10% 10% GND ≤ ≤ CY7C144, CY7C145 7C144-35 7C144-55 7C145-35 7C145-55 Unit Min Max Min Max 2.4 2.4 V 0.4 0.4 V 2.2 2.2 V ...
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... For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform. Document #: 38-06034 Rev. *E 7C144-15 7C144-25 7C144-35 7C145-15 7C145-25 7C145-35 Min Max Min Max Min less than t and t is less than t HZCE LZCE HZOE CY7C144, CY7C145 7C144-55 7C145-55 Unit Max Min Max LZOE Page [+] Feedback ...
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... SEM Flag Write to Read Time SWRD t SEM Flag Contention SPS Window Note 13. Test conditions used are Load 2. Document #: 38-06034 Rev. *E 7C144-15 7C144-25 7C144-35 7C145-15 7C145-25 7C145-35 Min Max Min Max Min CY7C144, CY7C145 7C144-55 7C145-55 Unit Max Min Max Page [+] Feedback ...
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... L, SEM = H when accessing RAM SEM = L when accessing semaphores. L 18. BUSY = HIGH for the writing port. 19 LOW Document #: 38-06034 Rev ACE t DOE DATA VALID t WC MATCH t PWE t SD VALID MATCH t WDD CY7C144, CY7C145 [14, 15] DATA VALID [14, 16, 17] t HZCE t HZOE t PD [18, 19 DDD VALID Page [+] Feedback ...
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... Data I/O pins enter high impedance when OE is held LOW during write. Document #: 38-06034 Rev SCE PWE t SD DATA VALID HIGH IMPEDANCE SCE PWE DATAVALID t HZWE HIGH IMPEDANCE allow the I/O drivers to turn off and data to be PWE HZWE SD CY7C144, CY7C145 [20, 21, 22 LZOE [20, 22, 23 LZWE Page [+] Feedback ...
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... SPS Document #: 38-06034 Rev VALID ADDRESS SCE SOP t SD DATA VALID PWE t SWRD t SOP READ CYCLE [25, 26, 27] Figure 11. Semaphore Contention MATCH t SPS MATCH = CE = HIGH L CY7C144, CY7C145 [24] t OHA t ACE DATA VALID OUT t DOE Page [+] Feedback ...
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... ADDRESS R R/W R DATAIN ADDRESS L BUSY L DATA OUTL Figure 13. Write Timing with Busy Input (M/S=LOW) R/W BUSY Document #: 38-06034 Rev. *E Figure 12. Read with BUSY (M/S=HIGH MATCH t PWE t SD VALID MATCH t BLA t WDD t PWE CY7C144, CY7C145 [19 BHA t BDD t DDD VALID Page [+] Feedback ...
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... BUSY will be asserted. PS Document #: 38-06034 Rev. *E ADDRESS MATCH BLC ADDRESS MATCH BLC ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA CY7C144, CY7C145 [28] t BHC t BHC [28] Page [+] Feedback ...
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... 30 depends on which enable pin (CE or R/W INS INR L Document #: 38-06034 Rev. *E Figure 16. Interrupt Timing Diagrams t WC WRITE 1FFF [29 [30] [30] t INR t WC WRITE 1FFE [29 [30] t [30] INR ) is asserted last. L CY7C144, CY7C145 t RC READ 1FFF t RC READ 1FFE Page [+] Feedback ...
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... TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 25.0 20.0 15.0 10 4. 25° 200 400 600 800 1000 CAPACITANCE (pF) CY7C144, CY7C145 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 200 160 120 25° 125 0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs ...
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... Ordering Information 8K x8 Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C144-15AC CY7C144-15AXC CY7C144-15JC CY7C144-15JXC CY7C144-15AI CY7C144-15JXI CY7C144-15AXI 25 CY7C144-25AC CY7C144-25AXC CY7C144-25JC CY7C144-25AI CY7C144-25JI 35 CY7C144-35AC CY7C144-35JC CY7C144-35AI CY7C144-35JI 55 CY7C144-55AC CY7C144-55AXC CY7C144-55JC CY7C144-55JXC CY7C144-55AI CY7C144-55JI 8K x9 Dual-Port SRAM 15 CY7C145-15AC CY7C145-15AXC CY7C145-15JC 25 CY7C145-25AC CY7C145-25JC CY7C145-25AI CY7C145-25JI 35 CY7C145-35AC ...
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... Package Diagrams Figure 18. 64-Pin Thin Plastic Quad Flat Pack ( 1.4 mm), 51-85046 Document #: 38-06034 Rev. *E CY7C144, CY7C145 51-85046 *C Page [+] Feedback ...
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... Package Diagrams (continued) Figure 19. 80-Pin Thin Plastic Quad Flat Pack, 51-85065 Figure 20. 68-Pin Plastic Leaded Chip Carrier, 51-85005 Document #: 38-06034 Rev. *E CY7C144, CY7C145 51-85065-*B 51-85005-*A Page [+] Feedback ...
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... Change from Spec number: 38-00163 to 38-06034 12/27/02 Power up requirements added to Maximum Ratings Information See ECN Removed cross information from features section, added CY7C144-15AI to ordering information section See ECN Added Pb-Free Logo Added Pb-Free parts to ordering information: CY7C144-15AXC, CY7C144-15JXC, CY7C144-15AXI, CY7C144-25AXC, ...