CY2SSTV16859ZC Cypress Semiconductor Corp, CY2SSTV16859ZC Datasheet - Page 4

• Manufacturer Part Number: CY2SSTV16859ZC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY2SSTV16859ZC

• Logic Family: SSTV
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Bits: 13
• Number Of Inputs: 13
• Number Of Outputs: 26
• High Level Output Current: -20mA
• Low Level Output Current: 20mA
• Package Type: TSSOP
• Propagation Delay Time: 5ns
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Mounting: Surface Mount
• Pin Count: 64
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-07463 Rev. *B
DC Electrical Specifications
AC Electrical Specifications
Table 2. Switching Characteristics Over Recommended Operating Conditions
I
r
r
r
C
f
t
t
t
t
t
f
t
t
Notes:
10. For data signal input slew rate ≥ 1 V/ns.
11. For data signal input slew rate ≥ V/ns and < 1V/ns.
12. CLK and CLK# signals input slew rates are ≥ 1 V/ns.
13. See test circuits and waveforms. TA = 0°C to +85°C.
Parameter
DDD
clock
w
act
inact
su
h
max
PHL
PD
OH
OL
O(∆)
Parameter
Parameter
i
Dynamic
operating – clock
only
Dynamic
operating – per
each data input
Output high
Output low
|r
separate bit
Data Inputs
CLK and CLK#
RESET#
Clock Frequency
Pulse duration, CLK, CLK# high or low
Differential inputs active time (data inputs must be held low after RESET# is taken high).
Differential inputs inactive time (data and clock inputs must be held at valid levels
(not floating) after RESET# is taken low).
Set-up time, fast slew rate
Set-up time, slow slew rate
Hold time, fast slew rate
Hold time, slow slew rate
RESET#
CLK and CLK#
OH
Description
– r
OL
| each
From (Input)
RESET# = V
CLK and CLK# switching 50% duty
cycle
RESET# = V
CLK and CLK# switching 50% duty
cycle. One data input switching at half
clock frequency, 50% duty cycles.
I
I
I
V
V
V
OH
OL
O
I
ICR
I
= V
= V
= 20 mA, T
= 20 mA
= –20 mA
= 1.25V, V
REF
DD
(continued)
[10, 12]
[11, 12]
[10, 12]
or V
[11, 12]
+ 310 mV
DD
DD
SS
A
, V
, V
= 25°C
I(PP)
Condition
I
I
Description
= V
= V
= 360 mV
IH(AC)
IH(AC)
or V
or V
IL(AC),
IL(AC),
To (Output)
Data before CLK↑, CLK#↓
Data after CLK ↑, CLK#↓
Q
Q
I
O
= 0
2.3 to 2.7V
2.3 to 2.7V
VDD
2.7V
2.5V
2.7
2.5
2.5
2.5
[13]
V
Min.
Min.
280
1.1
2.5
2.5
2.5
DD
–
–
7
7
–
= 2.5V ± 0.2V
V
DD
CY2SSTV16859
Min.
0.75
0.75
2.0
0.9
0.9
–
–
–
= 2.5V± 0.2V
Typ.
30.0
15.0
Max.
–
–
–
–
–
–
2.8
–
5
[9]
Max.
280
22
22
–
–
–
–
–
Max.
Page 4 of 8
3.5
3.5
3.5
20
20
–
–
4
MHz
Unit
ns
ns
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
clock
clock
Unit
MHz
MHz
/data
input
µA/
µA/
pF
pF
pF
Ω
Ω
Ω
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