CY7C1007B-15VI Cypress Semiconductor Corp, CY7C1007B-15VI Datasheet

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CY7C1007B-15VI

Manufacturer Part Number
CY7C1007B-15VI
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C1007B-15VI

Density
1Mb
Access Time (max)
15ns
Operating Supply Voltage (typ)
5V
Package Type
SOJ
Operating Temp Range
-40C to 85C
Supply Current
80mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
28
Word Size
1b
Lead Free Status / Rohs Status
Not Compliant
Cypress Semiconductor Corporation
Document #: 38-05030 Rev. **
Features
Functional Description
The CY7C107B and CY7C1007B are high-performance
CMOS static RAMs organized as 1,048,576 words by 1 bit.
Easy memory expansion is provided by an active LOW Chip
Enable (CE) and three-state drivers. These devices have an
automatic power-down feature that reduces power consump-
tion by more than 65% when deselected.
Selection Guide
• High speed
• CMOS for optimum speed/power
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
Maximum Access Time (ns)
Maximum Operating
Current (mA)
Maximum CMOS Standby
Current SB2 (mA)
Logic Block Diagram
— t
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
AA
= 12 ns
INPUT BUFFER
DECODER
COLUMN
512x2048
ARRA Y
POWER
DOWN
7C1007B-12
7C107B-12
12
90
2
3901 North First Street
7C1007B-15
7C107B-15
CE
WE
D
D
IN
OUT
15
80
107B-1
2
Writing to the devices is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the input pin
(D
dress pins (A
Reading from the devices is accomplished by taking Chip En-
able (CE) LOW while Write Enable (WE) remains HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the data output (D
pin.
The output pin (D
when the device is deselected (CE HIGH) or during a write
operation (CE and WE LOW).
The CY7C107B is available in a standard 400-mil-wide SOJ;
the CY7C1007B is available in a standard 300-mil-wide SOJ.
IN
) is written into the memory location specified on the ad-
7C1007B-20
7C107B-20
San Jose
20
75
0
2
through A
OUT
Pin Configuration
D
GND
) is placed in a high-impedance state
OUT
A
A
A
A
A
A
A
A
A
A
WE
NC
10
11
12
13
14
15
16
17
18
19
1M x 1 Static RAM
19
7C1007B-25
).
7C107B-25
CA 95134
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SOJ
25
70
2
Revised September 7, 2001
28
27
26
25
24
23
22
21
20
19
18
17
16
15
107B-2
CY7C1007B
V
A
A
A
A
A
A
NC
A
A
A
A
D
CE
CY7C107B
CC
9
8
7
6
5
4
3
2
1
0
IN
7C1007B-35
7C107B-35
408-943-2600
35
60
2
OUT
)

Related parts for CY7C1007B-15VI

CY7C1007B-15VI Summary of contents

Page 1

... The output pin (D when the device is deselected (CE HIGH) or during a write operation (CE and WE LOW). The CY7C107B is available in a standard 400-mil-wide SOJ; the CY7C1007B is available in a standard 300-mil-wide SOJ OUT CE WE ...

Page 2

... OUT 1/t MAX RC Max > > < MAX Max > V – 0.3V > V – 0. < 0.3V CY7C107B CY7C1007B Ambient [2] Temperature 0°C to +70°C 40°C to +85°C 7C107B-15 7C107B-20 7C1007B-15 7C1007B-20 Max. Min. Max. Min. 2.4 2.4 0 0.3 0.3 0.8 0.3 0.8 0 – ...

Page 3

... Max GND CC OUT V = Max mA, OUT 1/t MAX RC Max > > < MAX Max > V – 0.3V > V – 0. < 0.3V Test Conditions MHz 5.0V CC CY7C107B CY7C1007B 7C107B-35 7C1007B-35 Max. Min. Max. 2.4 0.4 0 0 0.8 0.3 0 300 300 Max. Unit Page Unit ...

Page 4

... JIG AND SCOPE (b) 107-3 1.73V 7C107B-12 7C107B-15 7C1007B-12 7C1007B-15 Min. Max. Min. Max less than t and t is less than t HZCE LZCE HZWE CY7C107B CY7C1007B ALL INPUT PULSES 3.0V 90% 10% GND 3 ns 7C107B-20 7C107B-25 7C107B-35 7C1007B-20 7C1007B-25 7C1007B-35 Min. Max. Min. Max. Min ...

Page 5

... No input may exceed V + 0.5V. CC 10. Device is continuously selected 11 HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW. Document #: 38-05030 Rev OHA ACE 50 SCE PWE DATA VALID CY7C107B CY7C1007B DATA VALID t HZCE IMPEDANCE DATA VALID 107-6 HIGH 107-7 107-8 Page ...

Page 6

... Switching Waveforms (continued) [13] Write Cycle No. 2 (WE Controlled) ADDRESS CE WE DATA IN DATA OUT Note: 13 goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05030 Rev SCE HZWE DATA UNDEFINED CY7C107B CY7C1007B PWE DATA VALID t LZWE HIGH IMPEDANCE 107-9 Page ...

Page 7

... L H Data Out L L High Z Ordering Information Speed (ns) Ordering Code 12 CY7C107B-12VC CY7C1007B-12VC 15 CY7C107B-15VC CY7C1007B-15VC 15 CY7C107B-15VI CY7C1007B-15VI 20 CY7C107B-20VC CY7C1007B-20VC 25 CY7C107B-25VC CY7C1007B-25VC Contact factory for “L” version availability. Package Diagrams Document #: 38-05030 Rev. ** Mode Power-Down Read Write Package Name Package Type V28 ...

Page 8

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 28-Lead (300-Mil) Molded SOJ V21 CY7C107B CY7C1007B Page ...

Page 9

... Document Title: CY7C107B/CY7C1007B Static RAM Document Number: 38-05030 Issue REV. ECN NO. Date ** 109950 12/02/01 Document #: 38-05030 Rev. ** Orig. of Change SZV Change from Spec number: 38-01116 to 38-05030 CY7C107B CY7C1007B Description of Change Page ...

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