CY7C1021-15VCT Cypress Semiconductor Corp, CY7C1021-15VCT Datasheet

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CY7C1021-15VCT

Manufacturer Part Number
CY7C1021-15VCT
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C1021-15VCT

Density
1Mb
Access Time (max)
15ns
Operating Supply Voltage (typ)
5V
Package Type
SOJ
Operating Temp Range
0C to 70C
Supply Current
220mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
44
Word Size
16b
Lead Free Status / Rohs Status
Not Compliant
Features
Functional Description
The CY7C1021 is a high-performance CMOS static RAM or-
ganized as 65,536 words by 16 bits. This device has an auto-
matic power-down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
Selection Guide
Cypress Semiconductor Corporation
Logic Block Diagram
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Shaded areas contain preliminary information.
• High speed
• CMOS for optimum speed/power
• Low active power
• Automatic power-down when deselected
• Independent Control of Upper and Lower bits
• Available in 44-pin TSOP II and 400-mil SOJ
A
A
A
A
A
A
A
A
— t
— 1320 mW (max.)
2
1
0
7
6
5
4
3
AA
= 12 ns
DATA IN DRIVERS
COLUMN DECODER
RAM Array
512 X 2048
64K x 16
Commercial
Commercial
L
3901 North First Street
(BLE) is LOW, then data from I/O pins (I/O
written into the location specified on the address pins (A
through A
from I/O pins (I/O
specified on the address pins (A
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the write
enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O
then data from memory will appear on I/O
truth table at the back of this data sheet for a complete descrip-
tion of read and write modes.
The input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1021 is available in standard 44-pin TSOP Type II
and 400-mil-wide SOJ packages.
7C1021-10
220
0.5
10
5
I/O
I/O
15
1
9
BHE
WE
CE
OE
BLE
San Jose
). If Byte High Enable (BHE) is LOW, then data
– I/O
– I/O
8
16
1
9
7C1021-12
to I/O
through I/O
64K x 16 Static RAM
220
0.5
12
5
8
I/O
I/O
I/O
I/O
V
I/O
I/O
I/O
I/O
V
Pin Configuration
A
A
A
A
WE
NC
CE
. If Byte High Enable (BHE) is LOW,
CC
A
A
A
A
A
SS
15
14
13
12
1
4
3
2
1
0
1
2
3
4
5
6
7
8
CA 95134
through I/O
SOJ / TSOP II
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
12
16
Top View
0
) is written into the location
7C1021-15
through A
220
0.5
15
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
5
16
CY7C1021
9
A
A
A
OE
BHE
BLE
I/O
I/O
I/O
I/O
V
V
I/O
I/O
I/O
I/O
NC
A
A
A
A
NC
) are placed in a
1
15
5
6
7
SS
CC
8
9
10
11
1021-2
to I/O
through I/O
16
15
14
13
12
11
10
9
).
408-943-2600
July 20, 2000
7C1021-20
16
. See the
220
0.5
20
5
8
), is
0

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CY7C1021-15VCT Summary of contents

Page 1

... HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1021 is available in standard 44-pin TSOP Type II and 400-mil-wide SOJ packages. I/O – I/O ...

Page 2

... < MAX , 5 CC – 0.3V 0.5 > V – 0.3V < 0.3V, f=0 IN Test Conditions MHz 5. CY7C1021 Ambient [2] Temperature + – + 7C1021-12 7C1021-15 7C1021-20 Max. Min. Max. Min. Max. 2.4 2.4 2.4 0.4 0.4 2.2 6.0 2.2 6.0 2.2 0.8 –0.3 0.8 –0.3 –1 +1 – ...

Page 3

... The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. R 481 5V 3. GND 255 < (b) 1021-3 167 1.73V 30 pF 7C1021-10 7C1021-12 Min. Max. Min less than less than t , and t HZCE LZCE HZOE LZOE 3 CY7C1021 ALL INPUT PULSES 90% 90% 10% 7C1021-15 7C1021-20 Max. Min. Max. Min. Max ...

Page 4

... Notes: 9. Device is continuously selected. OE, CE, BHE and/or BHE = V 10 HIGH for read cycle. 11. Address valid prior to or coincident with CE transition LOW OHA DOE t LZOE t DBE LZBE DATA VALID 50 CY7C1021 DATA VALID 1021-5 t HZOE t HZCE t HZBE HIGH IMPEDANCE ICC CC 50% I ISB SB 1021-6 ...

Page 5

... Write Cycle No. 2 (BLE or BHE Controlled) ADDRESS t SA BHE, BLE WE CE DATA I/O Notes: 12. Data I/O is high impedance BHE and/or BLE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state SCE PWE PWE t SCE CY7C1021 1021 1021-8 ...

Page 6

... Read - All bits High Z Read - Lower bits only Data Out Read - Upper bits only Data In Write - All bits High Z Write - Lower bits only Data In Write - Upper bits only High Z Selected, Outputs Disabled High Z Selected, Outputs Disabled 6 CY7C1021 LZWE 1021-10 Mode Power Standby ( Active ( ...

Page 7

... Ordering Information Speed (ns) Ordering Code 10 CY7C1021-10VC CY7C1021-10ZC CY7C1021L-10ZC 12 CY7C1021-12VC CY7C1021-12VI CY7C1021-12ZC 15 CY7C1021-15VC CY7C1021-15VI CY7C1021-15ZC CY7C1021-15ZI CY7C1021L-15ZC 20 CY7C1021-20VC CY7C1021-20ZC Shaded areas contain preliminary information. Document #: 38-00224-D Package Diagrams Package Name Package Type V34 44-Lead (400-Mil) Molded SOJ Z44 44-Lead TSOP Type II Z44 ...

Page 8

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 44-Pin TSOP II Z44 CY7C1021 51-85087-A ...

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