CY7C1021CV33-10ZI Cypress Semiconductor Corp, CY7C1021CV33-10ZI Datasheet

CY7C1021CV33-10ZI

Manufacturer Part Number
CY7C1021CV33-10ZI
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C1021CV33-10ZI

Density
1Mb
Access Time (max)
10ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
3.3V
Address Bus
16b
Package Type
TSOP-II
Operating Temp Range
-40C to 85C
Number Of Ports
1
Supply Current
90mA
Operating Supply Voltage (min)
2.97V
Operating Supply Voltage (max)
3.63V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Word Size
16b
Number Of Words
64K
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C1021CV33-10ZI
Manufacturer:
CY
Quantity:
481
Part Number:
CY7C1021CV33-10ZI
Manufacturer:
CYPRESS
Quantity:
20 000
Features
Cypress Semiconductor Corporation
Document Number: 38-05132 Rev. *H
Temperature ranges
Pin and function compatible with CY7C1021BV33
High speed
CMOS for optimum speed and power
Low active power: 325 mW (max)
Automatic power down when deselected
Independent control of upper and lower bits
Available in Pb-free and non Pb-free 44-pin 400 Mil SOJ, 44-pin
TSOP II and 48-Ball FBGA packages
Logic Block Diagram
Commercial: 0°C to 70°C
Industrial: –40°C to 85°C
Automotive-A: –40°C to 85°C
Automotive-E: –40°C to 125°C
t
t
AA
AA
= 8 ns (Commercial & Industrial)
= 12 ns (Automotive-E)
A
A
A
A
A
A
A
A
2
1
0
7
6
5
4
3
DATA IN DRIVERS
COLUMN DECODER
198 Champion Court
RAM Array
64K x 16
Functional Description
The CY7C1021CV33 is a high performance CMOS static RAM
organized as 65,536 words by 16 bits. This device has an
automatic power down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is
LOW, then data from IO pins (IO
location specified on the address pins (A
High Enable (BHE) is LOW, then data from IO pins (IO
IO
through A
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on IO
memory appears on IO
“Truth Table”
Write modes.
The input and output pins (IO
impedance state when the device is deselected (CE HIGH), the
outputs are disabled (OE HIGH), the BHE and BLE are disabled
(BHE, BLE HIGH), or during a write operation (CE LOW and WE
LOW).
For best practice recommendations, refer to the Cypress
application note
16
) is written into the location specified on the address pins (A
1
to IO
15
1-Mbit (64K x 16) Static RAM
San Jose
).
8
. If Byte High Enable (BHE) is LOW, then data from
on page 9 for a complete description of Read and
AN1064, SRAM System
,
CA 95134-1709
9
to IO
IO
IO
1
16
0
8
through IO
–IO
–IO
BHE
WE
CE
OE
BLE
1
. For more information, see the
through IO
7
15
CY7C1021CV33
Revised October 11, 2007
16
0
Guidelines.
through A
) are placed in a high
8
), is written into the
408-943-2600
15
9
). If Byte
through
0

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CY7C1021CV33-10ZI Summary of contents

Page 1

... Cypress Semiconductor Corporation Document Number: 38-05132 Rev. *H 1-Mbit (64K x 16) Static RAM Functional Description The CY7C1021CV33 is a high performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power down feature that significantly reduces power consumption when deselected. ...

Page 2

... Maximum CMOS Standby Current Pin Configuration Figure 1. 44-Pin SOJ/TSOP Note 1. NC pins are not connected on the die. Document Number: 38-05132 Rev - Comm’l/Ind’ Automotive-A Automotive-E Comm’l/Ind’l 5 Automotive-A Automotive-E [ BHE BLE CY7C1021CV33 -12 - [1] Figure 2. 48-Ball FBGA Pinout BLE BHE Unit Page ...

Page 3

... Control When LOW, the IO pins are allowed to behave as outputs. When deasserted HIGH, the IO pins are tri-stated and act as input data pins. Ground Ground for the device. Connected to ground of the system. Power Supply Power Supply Inputs to the Device. CY7C1021CV33 Description – – IO ...

Page 4

... Auto-E < MAX , Com’l/Ind’l CC – 0.3V, CC Auto-A > V – 0.3V Auto-E < 0.3V CY7C1021CV33 Ambient Temperature ( 0°C to +70°C –40°C to +85°C –40°C to +85°C –40°C to +125°C -10 -12 Max Min Max Min Max Min 2.4 2.4 2.4 ...

Page 5

... Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 Figure 3. AC Test Loads and Waveforms 50 Ω 30 pF* 1.5V (a) ALL INPUT PULSES 90% 10% (c) Fall Time: 1 V/ns CY7C1021CV33 . Max 8 8 SOJ TSOP II FBGA 65.06 76.92 95.32 34.21 15.86 10 ...

Page 6

... The input data setup and hold timing is referenced to the leading edge of the signal that terminates the write. Document Number: 38-05132 Rev -10 Min Max Min Max 100 100 values until the first memory access is performed less than less than t , and t HZCE LZCE HZOE LZOE AC Test Loads and CY7C1021CV33 -12 -15 Min Max Min Max 100 100 ...

Page 7

... WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. Document Number: 38-05132 Rev OHA Figure 5. Read Cycle No. 2 (OE Controlled ACE t DOE t LZOE t DBE t LZBE 50 CY7C1021CV33 [11, 12] DATA VALID [12, 13] t HZOE t HZCE t HZBE HIGH IMPEDANCE DATA VALID Page ...

Page 8

... WE CE DATA IO Notes 14. Data IO is high impedance if OE, BHE, and/or BLE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document Number: 38-05132 Rev. *H Figure 6. Write Cycle No. 1 (CE Controlled SCE PWE PWE t SCE . IH CY7C1021CV33 [14, 15 Page ...

Page 9

... Data Out Read – Upper Bits Only L Data In Data In Write – All Bits H Data In High Z Write – Lower Bits Only L High Z Data In Write – Upper Bits Only X High Z High Z Selected, Outputs Disabled H High Z High Z Selected, Outputs Disabled CY7C1021CV33 LZWE Mode Power Standby ( Active ( Active ( Active (I ...

Page 10

... Ordering Information Speed (ns) Ordering Code 8 CY7C1021CV33-8VXC CY7C1021CV33-8ZXC CY7C1021CV33-8BAXC 10 CY7C1021CV33-10VC CY7C1021CV33-10VXC CY7C1021CV33-10ZXC CY7C1021CV33-10ZI CY7C1021CV33-10ZXI CY7C1021CV33-10BAXI 12 CY7C1021CV33-12VC CY7C1021CV33-12VXC CY7C1021CV33-12ZXC CY7C1021CV33-12VI CY7C1021CV33-12VXI CY7C1021CV33-12ZXI CY7C1021CV33-12BAI CY7C1021CV33-12BAXI CY7C1021CV33-12VE CY7C1021CV33-12VXE CY7C1021CV33-12ZSE CY7C1021CV33-12ZSXE CY7C1021CV33-12BAE 15 CY7C1021CV33-15VXC CY7C1021CV33-15ZXC CY7C1021CV33-15ZI CY7C1021CV33-15ZXI CY7C1021CV33-15BAXI CY7C1021CV33-15ZSXA Document Number: 38-05132 Rev. *H Package Package Type Diagram ...

Page 11

... Package Diagrams Document Number: 38-05132 Rev. *H Figure 9. 44-Pin (400 Mil) Molded SOJ CY7C1021CV33 51-85082-*B Page ...

Page 12

... Package Diagrams (continued) Figure 10. 44-Pin Thin Small Outline Package Type II Document Number: 38-05132 Rev. *H CY7C1021CV33 51-85087-*A Page ...

Page 13

... Package Diagrams (continued) TOP VIEW PIN 1 CORNER (LASER MARK 7.00±0.10 SEATING PLANE C Document Number: 38-05132 Rev. *H Figure 11. 48-Ball FBGA ( 1.2 mm) 6 1.20 MAX. CY7C1021CV33 BOTTOM VIEW Ø0. Ø0. Ø0.30±0.05(48X 1.875 0.75 3.75 7.00±0.10 B 0.15(4X) PIN 1 CORNER 51-85096-*G Page ...

Page 14

... Document History Page Document Title: CY7C1021CV33, 1-Mbit (64K x 16) Static RAM Document Number: 38-05132 Issue Orig. of REV. ECN NO. Date Change ** 109472 12/06/01 HGK *A 115044 05/08/02 HGK *B 115808 06/25/02 HGK *C 120413 10/31/02 DFP *D 238454 See ECN RKF *E 334398 See ECN SYT *F 493565 ...

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