CY7C1021CV33-8ZC Cypress Semiconductor Corp, CY7C1021CV33-8ZC Datasheet

CY7C1021CV33-8ZC

Manufacturer Part Number
CY7C1021CV33-8ZC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C1021CV33-8ZC

Density
1Mb
Access Time (max)
8ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
3.3V
Address Bus
16b
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Number Of Ports
1
Supply Current
95mA
Operating Supply Voltage (min)
2.97V
Operating Supply Voltage (max)
3.63V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
44
Word Size
16b
Number Of Words
64K
Lead Free Status / Rohs Status
Not Compliant
Features
Cypress Semiconductor Corporation
Document Number: 38-05132 Rev. *I
Temperature ranges
Pin and function compatible with CY7C1021BV33
High speed
CMOS for optimum speed and power
Low active power: 325 mW (max)
Automatic power down when deselected
Independent control of upper and lower bits
Available in Pb-free and non Pb-free 44-pin 400 Mil SOJ, 44-pin
TSOP II and 48-Ball FBGA packages
Logic Block Diagram
Commercial: 0°C to 70°C
Industrial: –40°C to 85°C
Automotive-A: –40°C to 85°C
Automotive-E: –40°C to 125°C
t
t
t
AA
AA
AA
= 8 ns (Commercial)
= 10 ns (Industrial and Automotive-A)
= 12 ns (Automotive-E)
A
A
A
A
A
A
A
A
1
0
7
6
5
4
3
2
DATA IN DRIVERS
COLUMN DECODER
198 Champion Court
RAM Array
64K x 16
Functional Description
The CY7C1021CV33 is a high performance CMOS static RAM
organized as 65,536 words by 16 bits. This device has an
automatic power down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is
LOW, then data from IO pins (IO
location specified on the address pins (A
High Enable (BHE) is LOW, then data from IO pins (IO
IO
through A
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on IO
memory appears on IO
“Truth Table”
Write modes.
The input and output pins (IO
impedance state when the device is deselected (CE HIGH), the
outputs are disabled (OE HIGH), the BHE and BLE are disabled
(BHE, BLE HIGH), or during a write operation (CE LOW and WE
LOW).
For best practice recommendations, refer to the Cypress
application note
16
) is written into the location specified on the address pins (A
1
to IO
15
1-Mbit (64K x 16) Static RAM
San Jose
).
8
. If Byte High Enable (BHE) is LOW, then data from
on page 9 for a complete description of Read and
AN1064, SRAM System
,
CA 95134-1709
9
to IO
IO
IO
1
16
0
8
through IO
–IO
–IO
BHE
WE
CE
OE
BLE
1
. For more information, see the
through IO
7
15
CY7C1021CV33
Revised January 04, 2008
16
0
Guidelines.
through A
) are placed in a high
8
), is written into the
408-943-2600
15
9
). If Byte
through
0
[+] Feedback

Related parts for CY7C1021CV33-8ZC

CY7C1021CV33-8ZC Summary of contents

Page 1

... Cypress Semiconductor Corporation Document Number: 38-05132 Rev. *I 1-Mbit (64K x 16) Static RAM Functional Description The CY7C1021CV33 is a high performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power down feature that significantly reduces power consumption when deselected. ...

Page 2

... Maximum CMOS Standby Current Pin Configuration Figure 1. 44-Pin SOJ/TSOP Note 1. NC pins are not connected on the die. Document Number: 38-05132 Rev - Commercial 95 90 Industrial 90 Automotive-A 90 Automotive-E Commercial 5 5 Industrial 5 5 Automotive-A 5 Automotive-E [1] Figure 2. 48-Ball FBGA Pinout BLE OE BHE IO BLE CY7C1021CV33 - BHE Page Unit [+] Feedback ...

Page 3

... Control When LOW, the IO pins are allowed to behave as outputs. When deasserted HIGH, the IO pins are tri-stated and act as input data pins. Ground Ground for the Device. Connected to ground of the system. Power Supply Power Supply Inputs to the Device. CY7C1021CV33 Description – Page ...

Page 4

... Automotive-A < MAX Automotive-E , Commercial CC – 0.3V, CC Industrial > V – 0.3V, CC Automotive-A < 0.3V Automotive-E CY7C1021CV33 Ambient V Temperature ( 3.3V ± 10% 0°C to +70°C –40°C to +85°C –40°C to +85°C –40°C to +125°C -10 -12 -15 Min Max Min Max Min Max 2 ...

Page 5

... Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 Figure 3. AC Test Loads and Waveforms 10-, 12-, 15-ns devices: 50 Ω 30 pF* 1.5V (a) ALL INPUT PULSES 90% 10% (c) Fall Time: 1 V/ns CY7C1021CV33 . Max Unit 8 8 SOJ TSOP II FBGA 65.06 76.92 95.32 34.21 15.86 10 ...

Page 6

... CC is less than less than t , and t LZCE HZOE LZOE HZWE “AC Test Loads and Waveforms” CY7C1021CV33 -12 -15 Min Max Min Max 100 100 less than t for any given device. LZWE on page 5. Transition is measured ±500 ...

Page 7

... Device is continuously selected. OE, CE, BHE, and/or BLE = V 12 HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. Document Number: 38-05132 Rev OHA DOE t LZOE DBE DATA VALID 50 CY7C1021CV33 [11, 12] DATA VALID [12, 13] t HZOE t HZCE t HZBE HIGH IMPEDANCE 50 Page [+] Feedback ...

Page 8

... ADDRESS t SA BHE, BLE WE CE DATA IO Notes 14. Data IO is high impedance if OE, BHE, and/or BLE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document Number: 38-05132 Rev. *I [14, 15 SCE PWE PWE t SCE CY7C1021CV33 Page [+] Feedback ...

Page 9

... Data Out Read – Upper Bits Only Data In Data In Write – All Bits Data In High Z Write – Lower Bits Only High Z Data In Write – Upper Bits Only High Z High Z Selected, Outputs Disabled High Z High Z Selected, Outputs Disabled CY7C1021CV33 LZWE Power Standby ( Active ( Active (I ) ...

Page 10

... CY7C1021CV33-12ZXC 51-85087 44-pin TSOP Type II (Pb-free) CY7C1021CV33-12BAI 51-85096 48-ball FBGA CY7C1021CV33-12VXE 51-85082 44-pin (400-Mil) Molded SOJ (Pb-free) CY7C1021CV33-12ZSXE 51-85087 44-pin TSOP Type II (Pb-free) 15 CY7C1021CV33-15ZXC 51-85087 44-pin TSOP Type II (Pb-free) CY7C1021CV33-15ZSXA 51-85087 44-pin TSOP Type II (Pb-free) The 44 pin TSOP II package containing the Automotive grade device is designated as “ZS”, while the same package containing the Commercial/Industrial grade device is “ ...

Page 11

... Package Diagrams Document Number: 38-05132 Rev. *I Figure 9. 44-Pin (400 Mil) Molded SOJ CY7C1021CV33 51-85082-*B Page [+] Feedback ...

Page 12

... Package Diagrams (continued) Figure 10. 44-Pin Thin Small Outline Package Type II Document Number: 38-05132 Rev. *I CY7C1021CV33 51-85087-*A Page [+] Feedback ...

Page 13

... Package Diagrams (continued) TOP VIEW PIN 1 CORNER (LASER MARK 7.00±0.10 SEATING PLANE C Document Number: 38-05132 Rev. *I Figure 11. 48-Ball FBGA ( 1.2 mm) A 1.20 MAX. CY7C1021CV33 BOTTOM VIEW PIN 1 CORNER Ø0. Ø0. Ø0.30±0.05(48X 1.875 0.75 3.75 7.00±0.10 B 0.15(4X) 51-85096-*G Page ...

Page 14

... Document History Page Document Title: CY7C1021CV33, 1-Mbit (64K x 16) Static RAM Document Number: 38-05132 Issue Orig. of REV. ECN NO. Date Change ** 109472 12/06/01 HGK *A 115044 05/08/02 HGK *B 115808 06/25/02 HGK *C 120413 10/31/02 DFP *D 238454 See ECN RKF *E 334398 See ECN SYT *F 493565 ...

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