CY7C1324-117AC Cypress Semiconductor Corp, CY7C1324-117AC Datasheet
CY7C1324-117AC
Specifications of CY7C1324-117AC
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CY7C1324-117AC Summary of contents
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... Pentium is a registered trademark of Intel Corporation. Cypress Semiconductor Corporation 3.3V 128K x 18 Synchronous Functional Description The CY7C1324 is a 3.3V, 128K by 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter cap- tures the first address in a burst and increments the address automatically for the rest of the burst access ...
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... Pin Configuration DDQ DDQ BYTE1 DDQ DDQ 100-Lead TQFP CY7C1324 CY7C1324 DDQ DDQ BYTE0 DDQ DDQ ...
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... The device must be deselected prior to entering the “sleep” mode. CE main inactive for the duration of t turns low 3 CY7C1324 after clock rise. ADSP is CDV is HIGH. Second Third Fourth Address Address ...
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... OE is asynchronous and is not sampled with the clock rise. During a read cycle DQ=High-Z when OE is inactive, and DQ=data when OE is active ADSP ADSP CY7C1324 ADV WE OE CLK L-H High L-H High L-H High L-H High L-H High HIGH L L-H High L L L-H High L L-H High L L-H High L-H High L L-H High L L-H D Writes may occur only on subsequent clocks [1:0]. ...
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... Bidirectional Data Parity lines. These behave identical to DQ These signals can be used as parity bits for bytes 0 and 1 respectively. Power supply inputs to the core of the device. Should be connected to 3.3V power supply. 5 CY7C1324 are also loaded into the burst [1:0] are also loaded into the burst [1:0] ...
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... Do not use pins. Should be left unconnected or tied LOW Test Conditions ZZ > > < 0.2V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... >200 mA Operating Range Ambient Range Temperature Com’ + 0. 0. CY7C1324 BWE BWS BWS Min Max Unit 0. ...
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... IN DDQ IN 10-ns cycle, 100 MHz f=f inputs switching MAX, 11-ns cycle, 90 MHz 20-ns cycle, 50 MHz Max Device Deselected, All speeds f=0, inputs static Test Conditions MHz 5. CY7C1324 7C1324 Min. Max. Unit 2.4 V 1.7 V 0.4 V 0 0.3V –0.3 0 – – – ...
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... OH OL (min). CLZ 8 CY7C1324 ALL INPUT PULSES 90% 90% 10% 10% 2.5 ns -100 -90 -50 Max. Min. Max. Min. Max. Unit 11 20 4.5 4.5 4.5 4.5 2.0 2.0 0.5 ...
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... GW to define a write cycle (see Write Cycle Descriptions table). [3:0] 15. WDx stands for Write Data to Address X. B urst W rite ADSP ignored with CE inactive masks ADSP UNDEFINED = DON’T CARE 9 CY7C1324 Pipelined Write Unselected ADSC initiated write WD3 Unselected with CE 2 High-Z 3a ...
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... EOV t OEHZ t CDV Data Out CLZ Note: 16. RDx stands for Read Data from Address X. Burst Read ADSP ignored with Suspend Burst ADH masks ADSP DOH DON’T CARE = UNDEFINED 10 CY7C1324 Unselected Pipelined Read inactive 1 ADSC initiated read RD3 Unselected with CHZ ...
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... CE1 HIGH t EOHZ Q(B) D(C) (B+2) (B+1) (B+3) and GW to define a write cycle (see Write Cycle Definitions table). [1:0] and CE . All chip selects need to be active in order to select DON’T CARE = UNDEFINED 11 CY7C1324 ADH t CEH t CEH t WEH Q(D) (C+1) (C+2) (C+3) t DOH ...
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... RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data- stands for Data-out CYC ADH t CEH t WES ADSP ignored with CE HIGH 1 Q(D) and CE . All chip selects need to be active in order to select UNDEFINED = DON’T CARE 12 CY7C1324 WEH D (E) D (F) D (H) D (G) D(C) t DOH t CHZ ...
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... Timing Diagrams (continued) OE Switching Waveforms OE t EOHZ three-state I/Os t EOV t EOLZ 13 CY7C1324 ...
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... CLK ADSP HIGH ADSC CE 1 LOW CE 2 HIGH I/Os Notes: 17. Device must be deselected when entering ZZ mode. See Cycle Description table for all possible signal conditions to deselect the device. 18. I/Os are in three-state when exiting ZZ sleep mode. t ZZS I (active CCZZ Three-state 14 CY7C1324 t ZZREC ...
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... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Name Package Type A101 100-Lead Thin Quad Flat Pack A101 100-Lead Thin Quad Flat Pack A101 100-Lead Thin Quad Flat Pack A101 100-Lead Thin Quad Flat Pack CY7C1324 Operating Range Commercial Commercial Commercial Commercial 51-85050-A ...