CY7C1345B-100BGC Cypress Semiconductor Corp, CY7C1345B-100BGC Datasheet
CY7C1345B-100BGC
Specifications of CY7C1345B-100BGC
Related parts for CY7C1345B-100BGC
CY7C1345B-100BGC Summary of contents
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... Intel and Pentium are registered trademarks of Intel Corporation. Cypress Semiconductor Corporation Functional Description The CY7C1345B is a 3.3V, 128K by 36 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter cap- tures the first address in a burst and increments the address automatically for the rest of the burst access ...
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... Pin Configurations DDQ V 5 SSQ BYTE2 SSQ V 11 DDQ DDQ V 21 SSQ BYTE3 SSQ V 27 DDQ 100-Pin TQFP CY7C1345B CY7C1345B DDQ V SSQ BYTE1 10 V SSQ V DDQ DDQ V SSQ BYTE0 SSQ V DDQ ...
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... When ADSP and [1:0] to select one of the 64K address locations. Sampled [1: and CE are sampled active, and ADSP or ADSC is active controls DQ and controls DQ 0 [7: controls DQ and DP . See Write Cycle Description table for further details. 3 [31:24] 3 gates ADSP select/deselect the device CY7C1345B DDQ DQP ...
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... Maximum access delay from the clock rise ( 7.5 ns (117-MHz device). CDV The CY7C1345B supports secondary cache in systems utiliz- ing either a linear or interleaved burst sequence. The inter- leaved burst order supports Pentium and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence ...
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... OE. Burst Sequences The CY7C1345B provides an on-chip 2-bit wraparound burst counter inside the SRAM. The burst counter is fed by A and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE will select a linear burst sequence ...
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... OE is asynchronous and is not sampled with the clock rise. During a read cycle DQ=High-Z when OE is inactive, and DQ=data when OE is active ADSP ADSC CY7C1345B ADV WE OE CLK L-H High L-H High L-H High L-H High L-H High High L L-H High L L L-H High L L-H High L L-H High L-H High L L-H High L L-H D Writes may occur only on subsequent clocks [3:0]. ...
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... Min. ZZ > > < 0.2V 2t CYC Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... >200 mA Operating Range Ambient Range Temperature Com’l 0°C to +70°C + 0.5V Ind’l –40°C to +85° 0. CY7C1345B ...
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... IN IN DDQ inputs static Max Device Deselected – 0. 0.3V, IN DDQ inputs switching MAX Max Device Deselected –0. 0.3V inputs static 8 CY7C1345B Min. Max. 2.4 2.0 0.4 0.7 2 0.3V 1 0.3V –0.3 0.8 –0.3 0 –30 5 –5 30 –5 5 –300 8.5-ns cycle, 117 MHz ...
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... DD R1=317 3.3V 3.0V R2=351 GND 5 pF INCLUDING Rise Time: 1 V/ns JIG AND SCOPE (b) [9] Description [10, 12] [10, 12] (min.). CLZ 9 CY7C1345B Max. Unit 4.0 pF 4.0 pF ALL INPUT PULSES 90% 90% 10% 10% Fall Time: 1 V/ns -117 -100 Min. Max. Min. Max. Unit 8 ...
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... GW to define a write cycle (see Write Cycle Descriptions table). [3:0] 14. WDx stands for Write Data to Address X. B urst W rite ADSP ignored with CE inactive masks ADSP UNDEFINED = DON’T CARE 10 CY7C1345B Pipelined Write Unselected ADSC initiated write WD3 Unselected with CE 2 High-Z 3a ...
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... EOV t OEHZ t CDV Data Out CLZ Note: 15. RDx stands for Read Data from Address X. Burst Read ADSP ignored with Suspend Burst ADH masks ADSP DOH DON’T CARE = UNDEFINED 11 CY7C1345B Unselected Pipelined Read inactive 1 ADSC initiated read RD3 Unselected with CHZ ...
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... ADSP ignored with CE HIGH Q(B) (B+2) (B+1) (B+3) , and GW to define a write cycle (see Write Cycle Descriptions table). [1:0] and CE . All chip selects need to be active in order to select UNDEFINED = DON’T CARE 12 CY7C1345B ADH t CEH t CEH t WEH EOHZ D(C) (C+1) (C+2) (C+3) ...
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... ADSP initiated Reads ADSP ADV t CES CLZ Data In/Out Out Out Out t CDV Back to Back Reads CYC CL CH WD1 t ADH t CEH t WES ADSP ignored with CE HIGH Out In t DOH Back to Back Writes = UNDEFINED = DON’T CARE 13 CY7C1345B WD2 WD3 WD4 t WEH D( CHZ ...
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... Timing Diagrams (continued) OE Switching Waveforms OE t EOHZ I/Os t EOV three-state t EOLZ 14 CY7C1345B ...
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... CLK ADSP HIGH ADSC CE 1 LOW CE 2 HIGH I/Os Notes: 16. Device must be deselected when entering ZZ mode. See Cycle Description Table for all possible signal conditions to deselect the device. 17. I/Os are in three-state when exiting ZZ sleep mode. t ZZS I (active CCZZ Three-state 15 CY7C1345B t ZZREC ...
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... Ordering Information Speed (MHz) Ordering Code 117 CY7C1345B-117AC CY7C1345B-117BGC 100 CY7C1345B-100AC CY7C1345B-100BGC CY7C1345B-100AI CY7C1345B-100BGI Document #: 38-00953-*B Package Diagram 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 Package Name Package Type A101 100-Lead Thin Quad Flat Pack BG119 119-Ball BGA A101 100-Lead Thin Quad Flat Pack ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 119-Lead FBGA ( 2.4 mm) BG119 CY7C1345B 51-85115 ...