CY7C1364B-166AC Cypress Semiconductor Corp, CY7C1364B-166AC Datasheet
CY7C1364B-166AC
Specifications of CY7C1364B-166AC
Related parts for CY7C1364B-166AC
CY7C1364B-166AC Summary of contents
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... Cypress Semiconductor Corporation Document #: 38-05420 Rev. ** 9-Mb (256K x 32) Pipelined Sync SRAM Functional Description The CY7C1364B SRAM integrates 262,144 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK) ...
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... V 10 SSQ V 11 DDQ DDQ V 21 SSQ BYTE SSQ V 27 DDQ Document #: 38-05420 Rev. ** 200 MHz 3.0 220 100-pin TQFP CY7C1339F CY7C1364B 166 MHz Unit 3.5 ns 180 DDQ SSQ B BYTE SSQ DDQ DDQ SSQ A A BYTE SSQ DDQ A A Page [+] Feedback ...
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... CLK. As outputs, they deliver the data contained in the memory location specified by “A” during the previous clock rise of the Read cycle. The direction of the pins is controlled When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ are placed in a three-state condition. CY7C1364B , CE , and CE 1 ...
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... Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1364B is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so will three-state the output drivers. ...
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... Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1364B is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so will three-state the output drivers. ...
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... ,BW ,BW ,BW ) and BWE = WRITE = H when all Byte Write Enable signals CY7C1364B DQ Write ADV Three-State Three-State Three-State Three-State Three-State Three-State Three-State Read L H Three-State Read Read L H Three-State Read Read H H Three-State Read Read H H Three-State Read Read H X Three-State Write ...
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... Write Byte C – Write Bytes C, A Write Bytes C, B Write Bytes Write Byte D – Write Bytes D, A Write Bytes D, B Write Bytes Write Bytes D, C Write Bytes Write Bytes Write All Bytes Write All Bytes Document #: 38-05420 Rev BWE CY7C1364B Page [+] Feedback ...
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... Max., Device Deselected, All speeds DD ≥ V ≤ /2), undershoot: V (AC) > –2V (Pulse width less than t CYC IL (min.) within 200 ms. During this time V < V and CY7C1364B Ambient Temperature DDQ 0°C to +70°C 3.3V 3.3V –5% –5%/+10 Min. Max. Unit 3.135 3.6 3.135 ...
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... EIA/JESD51 Description T = 25° MHz 3.3V 3.3V DDQ R = 317Ω 3.3V V OUTPUT GND 351Ω INCLUDING JIG AND (b) SCOPE CY7C1364B TQFP Package Unit °C/W 25 °C/W 9 Test Conditions Max. Unit ALL INPUT PULSES DD 90% 90% 10% 10% ≤ ≤ (c) Page ...
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... Set-up before CLK Rise Hold after CLK Rise is the time that the power needs to be supplied above V and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ CY7C1364B -200 -166 Max. Min. Max. Unit ...
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... OEV OEHZ t OELZ t DOH Q(A2 Q(A1) BURST READ DON’T CARE UNDEFINED is HIGH and CE is LOW. When CE is HIGH CY7C1364B A3 Burst continued with new base address Deselect cycle t CHZ Q( Q(A2) Q( Burst wraps around to its initial state is HIGH LOW HIGH ...
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... Full width Write can be initiated by either GW LOW HIGH, BWE LOW and BW Document #: 38-05420 Rev WES t WEH ADV suspends burst D(A2 BURST WRITE DON’T CARE UNDEFINED LOW CY7C1364B ADSC extends burst t ADS t ADH A3 t WES t WEH t t ADVS ADVH D( D(A3 ...
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... The data bus (Q) remains in High-Z following a Write cycle unless an ADSP , ADSC , or ADV cycle is performed. 20 HIGH. Document #: 38-05420 Rev WES t WEH OELZ D(A3) Q(A4) Q(A4+1) Single WRITE BURST READ DON’T CARE UNDEFINED CY7C1364B A5 A6 D(A5) D(A6) Q(A4+2) Q(A4+3) Back-to-Back WRITEs Page [+] Feedback ...
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... Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 22. DQs are in High-Z when exiting ZZ sleep mode. Ordering Information Speed (MHz) Ordering Code 166 CY7C1364B-166AC Please contact your local Cypress sales representative for availability of 200-MHz speed grade option. Document #: 38-05420 Rev. ** High-Z DON’T CARE Package Name ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1364B 51-85050-A ...
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... Document History Page Document Title: CY7C1364B 9-Mb (256K x 32) Pipelined Sync SRAM Document Number: 38-05420 REV. ECN NO. Issue Date ** 200661 See ECN Document #: 38-05420 Rev. ** Orig. of Change Description of Change NJY New Data Sheet CY7C1364B Page [+] Feedback ...