CY7C1399BL-12VC Cypress Semiconductor Corp, CY7C1399BL-12VC Datasheet

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CY7C1399BL-12VC

Manufacturer Part Number
CY7C1399BL-12VC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C1399BL-12VC

Density
256Kb
Access Time (max)
12ns
Operating Supply Voltage (typ)
3.3V
Package Type
SOJ
Operating Temp Range
0C to 70C
Supply Current
55mA
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
28
Word Size
8b
Lead Free Status / Rohs Status
Not Compliant
Cypress Semiconductor Corporation
Document #: 38-05071 Rev. *C
Features
Functional Description
The CY7C1399B is a high-performance 3.3V CMOS Static
RAM organized as 32,768 words by 8 bits. Easy memory ex-
pansion is provided by an active LOW Chip Enable (CE) and
Selection Guide
Note:
1.
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current ( A)
• Single 3.3V power supply
• Ideal for low-voltage cache memory applications
• High speed
• Low active power
• Low-power alpha immune 6T cell
• Plastic SOJ and TSOP packaging
Logic Block Diagram
— 10/12/15 ns
— 216 mW (max.)
For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
CE
WE
OE
A
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
9
[1]
INPUT BUFFER
DECODER
32K x 8
ARRAY
COLUMN
3901 North First Street
POWER
DOWN
L
1399B-10
500
10
60
50
active LOW Output Enable (OE) and three-state drivers. The
device has an automatic power-down feature, reducing the
power consumption by more than 95% when deselected.
An active LOW Write Enable signal (WE) controls the writing/
reading operation of the memory. When CE and WE inputs are
both LOW, data on the eight data input/output pins (I/O
through I/O
the address present on the address pins (A
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con-
tents of the location addressed by the information on address
pins is present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. The CY7C1399B is available in 28-pin standard
300-mil-wide SOJ and TSOP Type I packages.
7
San Jose
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
) is written into the memory location addressed by
32K x 8 3.3V Static RAM
1399B-12
0
1
2
3
4
5
6
7
500
12
55
50
CA 95134
Pin Configurations
1399B-15
GND
I/O
I/O
I/O
A
A
A
A
A
A
A
A
A
A
10
11
12
13
14
5
6
7
8
9
0
1
2
500
15
50
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Top View
Revised June 19, 2001
SOJ
CY7C1399B
28
27
26
25
24
23
22
21
20
19
18
17
16
15
0
408-943-2600
I/O
V
WE
A
A
A
A
OE
A
CE
I/O
I/O
I/O
I/O
through A
1399B-20
CC
4
3
2
1
0
7
6
5
4
3
500
20
45
50
14
).
0

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CY7C1399BL-12VC Summary of contents

Page 1

... Maximum CMOS Standby Current ( A) Note: 1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05071 Rev. *C 32K x 8 3.3V Static RAM active LOW Output Enable (OE) and three-state drivers. The device has an automatic power-down feature, reducing the power consumption by more than 95% when deselected ...

Page 2

Pin Configuration ...

Page 3

Electrical Characteristics Over the Operating Range (continued) Parameter Description V Output HIGH Voltage OH V Output LOW Voltage OL V Input HIGH Voltage IH V Input LOW Voltage IL I Input Load Current IX I Output Leakage Current OZ I ...

Page 4

Switching Characteristics Over the Operating Range Parameter Read Cycle t Read Cycle Time RC t Address to Data Valid AA t Data Hold from Address Change OHA t CE LOW to Data Valid ACE t OE LOW to Data Valid ...

Page 5

Switching Characteristics Over the Operating Range Parameter Read Cycle t Read Cycle Time RC t Address to Data Valid AA t Data Hold from Address Change OHA t CE LOW to Data Valid ACE t OE LOW to Data Valid ...

Page 6

Data Retention Waveform Switching Waveforms [11, 12] Read Cycle No. 1 ADDRESS DATA OUT PREVIOUS DATA VALID [12, 13] Read Cycle No HIGH IMPEDANCE DATA OUT t LZCE SUPPLY CURRENT ...

Page 7

Switching Waveforms (continued) [9, 14, 15] Write Cycle No. 1 (WE Controlled) ADDRESS NOTE 16 DATA I/O t HZOE [9, 14, 15] Write Cycle No. 2 (CE Controlled) ADDRESS CE WE DATA I/O Write Cycle ...

Page 8

... H H High Z l product and comany names mentioned in this document may be the trademarks of their respective holders. Ordering Information Speed (ns) Ordering Code 10 CY7C1399B-10VC CY7C1399B-10ZC CY7C1399BL-10VC CY7C1399BL-10ZC 12 CY7C1399B-12VC CY7C1399B-12ZC CY7C1399BL-12VC CY7C1399BL-12ZC CY7C1399B-12VI CY7C1399B-12ZI 15 CY7C1399B-15VC CY7C1399B-15ZC CY7C1399BL-15VC CY7C1399BL-15ZC CY7C1399B-15VI CY7C1399B-15ZI 20 CY7C1399B-20VC CY7C1399B-20ZC CY7C1399BL-20VC CY7C1399BL-20ZC ...

Page 9

... Document #: 38-05071 Rev. *C © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...

Page 10

Document History Page Document Title: CY7C1399B 32K x 8 3.3V Static RAM Document Number: 38-05071 ISSUE REV. ECN NO. DATE ** 107264 05/25/01 *A 107533 06/28/01 *B 116472 09/17/02 *C 224340 See ECN Document #: 38-05071 Rev. *C ORIG. OF ...

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