CY7C4275-10ASI Cypress Semiconductor Corp, CY7C4275-10ASI Datasheet - Page 17

• Manufacturer Part Number: CY7C4275-10ASI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4275-10ASI

• Configuration: Dual
• Density: 576Kb
• Access Time (max): 8ns
• Word Size: 18b
• Organization: 32Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 55mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Not Compliant

Width Expansion Configuration
The CY7C4275/85 can be expanded in width to provide word
widths greater than 18 in increments of 18. During width ex-
pansion mode all control line inputs are common and all flags
are available. Empty (Full) flags should be created by ANDing
Document #: 38-06008 Rev. *A
FULL FLAG (FF)
DATA IN (D)
PROGRAMMABLE(PAE)
HALF FULL FLAG (HF)
Figure 1. Block Diagram of 32K x18/64K x 18 Deep Sync FIFO Memory Used in a Width Expansion Configuration
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
36
18
READ EXPANSION IN (RXI)
FF
RESET (RS)
7C4275
7C4285
EF
FIRST LOAD (FL)
18
18
WRITE EXPANSION IN (WXI)
the Empty (Full) flags of every FIFO; the PAE and PAF flags
can be detected from any one device. This technique will avoid
reading data from, or writing data to the FIFO that is “stag-
gered” by one clock cycle due to the variations in skew be-
tween RCLK and WCLK. Figure 1 demonstrates a 36-word width
by using two CY7C4275/85s.
FF
RESET (RS)
7C4275
7C4285
EF
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAF)
18
DATA OUT (Q)
EMPTY FLAG (EF)
4275–24
CY7C4275
CY7C4285
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