CY7C63000A-SC Cypress Semiconductor Corp, CY7C63000A-SC Datasheet

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CY7C63000A-SC

Manufacturer Part Number
CY7C63000A-SC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C63000A-SC

Cpu Family
enCoRe II
Device Core
M8C
Device Core Size
8b
Frequency (max)
12MHz
Interface Type
USB
Program Memory Type
EPROM
Program Memory Size
2KB
Total Internal Ram Size
128Byte
# I/os (max)
12
Number Of Timers - General Purpose
1
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4V
Instruction Set Architecture
RISC
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
20
Package Type
SOIC
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C63000A-SC
Manufacturer:
CYP
Quantity:
3 158
Part Number:
CY7C63000A-SC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Cypress Semiconductor Corporation
Document #: 38-08026 Rev. *A
1.0
Logic Block Diagram
• Low-cost solution for low-speed USB peripherals such
• USB Specification Compliance
• 8-bit RISC microcontroller
• Internal memory
as mouse, joystick, and gamepad
— Conforms to USB 1.5-Mbps Specification,
— Supports one device address and two endpoints
— Harvard architecture
— 6-MHz external ceramic resonator
— 12-MHz internal operation
— USB optimized instruction set
— 128 bytes of RAM
— 4 Kbytes of EPROM
Version 1.1
(one control endpoint and one data endpoint)
Features
CERAMIC RESONATOR
2/4 KByte
on Reset
EPROM
Power-
Timer
Watch
Dog
6-MHz
OSC
Interrupt
Controller
RISC
8-bit
core
INSTANT-ON
NOW™
R/C
EXT
3901 North First Street
Engine
D+,D–
V
USB
CC
/V
Universal Serial Bus Microcontroller
SS
128-Byte
RAM
P0.0–P0.7
• 8-bit free-running timer
• Watchdog timer (WDT)
• Internal power-on reset (POR)
• Instant-On Now™ for Suspend and Periodic Wake-up
• Improved output drivers to reduce EMI
• Operating voltage from 4.0V to 5.25 VDC
• Operating temperature from 0–70°C
• Available in space saving and low-cost 20-pin PDIP,
• Industry-standard programmer support
PORT
Modes
20-pin SOIC, and 24-pin QSOP packages
— Integrated USB transceiver
— Up to 16 Schmitt trigger I/O pins with internal pull-up
— Up to eight I/O pins with LED drive capability
— Special purpose I/O mode supports optimization of
— Maskable Interrupts on all I/O pins
0
photo transistor and LED in mouse application
Timer
8-bit
P1.0–P1.7
San Jose
PORT
1
,
CA 95134
Revised October 5, 2004
CY7C63001A
CY7C63101A
408-943-2600

Related parts for CY7C63000A-SC

CY7C63000A-SC Summary of contents

Page 1

... Reset Interrupt Controller Watch Dog Timer Cypress Semiconductor Corporation Document #: 38-08026 Rev. *A Universal Serial Bus Microcontroller — Integrated USB transceiver — Schmitt trigger I/O pins with internal pull-up — eight I/O pins with LED drive capability — Special purpose I/O mode supports optimization of photo transistor and LED in mouse application — ...

Page 2

Pin Configurations 20-pin DIP/SOIC P0.4 P0 P0.1 19 P0.5 2 P0.6 P0 P0.7 P0 P1.1 P1 P1.2 P1 D– ...

Page 3

Pin Definitions (continued) Name I/O 20-Pin CEXT I I/O 14 D– I – – – 5.0 Pin Description Name V One pin. Connects to the USB power ...

Page 4

... Interrupt Vector – GPIO 0x000E Interrupt Vector – Cext 0x0010 On-chip program Memory 0x07FF 2K ROM (CY7C63000A, CY7C63100A) 0x0FFF 4K ROM (CY7C63001A, CY7C63101A) Figure 6-1. Program Memory Space The DSP pre-decrements by one whenever a PUSH instruction is executed and it increments by one after a POP instruction is used. The default value of the DSP after reset is 0x00, which would cause the first PUSH to write into USB FIFO space for Endpoint 1 ...

Page 5

DSP user firmware DSP 6.2 I/O Register Summary I/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions. Table 6-1. I/O Register Summary Register Name I/O Address P0 Data 0x00 P1 Data 0x01 ...

Page 6

Table 6-1. I/O Register Summary (continued) Register Name I/O Address P1 Isink 0x38-0x3F SCR 0xFF 6.3 Reset The USB Controller supports three types of resets. All registers are restored to theirWatchdog default states during a reset. The USB Device Address ...

Page 7

Last write to Watchdog Timer Register 6.3.2 Watchdog Reset (WDR) The Watchdog Timer Reset (WDR) occurs when the Most Significant Bit of the 4-bit Watchdog Timer Register transitions from LOW to HIGH. Writing any value to ...

Page 8

On-Chip Timer The USB Controller is equipped with a free-running timer driven by a clock one-sixth the resonator frequency. Bits 0 through 7 of the counter are readable from the read-only Timer Register located at I/O address 0x23. The ...

Page 9

Each GPIO line includes an internal R provides both the pull-up function and slew control. Two factors govern the enabling and disabling of each resistor: the state of its associated Port Pull-up register bit and the state of the Data ...

Page 10

PULL1.7 PULL1.6 PULL1 Figure 6-12. Port 1 Pull-up Register (Address 0x09) Writing a “0” to the Data Register drives the output LOW. Instead of providing a fixed output drive, the USB Controller allows the ...

Page 11

When servicing an interrupt, the hardware first disables all interrupts by clearing the Global Interrupt Enable Register. Next, the interrupt latch of the current interrupt is cleared. This is followed by a CALL instruction to the ROM address associated with ...

Page 12

GPIO Interrupt The General Purpose I/O interrupts are generated by signal transitions at the Port 0 and Port 1 I/O pins. GPIO interrupts are edge sensitive with programmable interrupt polarities. Setting a bit HIGH in the Port Pull-up Register ...

Page 13

USB Interrupt A USB Endpoint 0 interrupt is generated after the host has written data to Endpoint 0 or after the USB Controller has transmitted a packet from Endpoint 0 and receives an ACK from the host. An OUT ...

Page 14

Endpoint 0 All USB devices are required to have an endpoint number 0 that is used to initialize and manipulate the device. Endpoint 0 provides access to the device’s configuration information and allows generic USB status and control accesses. ...

Page 15

Endpoint 0 Transmit The USB Endpoint 0 TX Register located at I/O address 0x10 controls data transmission from Endpoint 0 (see Figure 6-22). This is a read/write register. All bits are cleared during reset INEN DATA1/0 STALL ...

Page 16

The data is not written into the FIFO when this bit is set. This bit is cleared when a SETUP token is received by Endpoint 0. Bit 4 is used to enable the receiving of Endpoint 0 OUT packets. When ...

Page 17

Figure 6-26. Differential Input Sensitivity Over Entire Common Mode Range 6.11 External USB Pull-Up Resistor The USB system specifies that a pull-up resistor be connected on the D– pin of low-speed ...

Page 18

Instruction Set Summary Table 6-5. Instruction Set Map MNEMONIC operand HALT ADD A,expr data ADD A,[expr] direct ADD A,[X+expr] index ADC A,expr data ADC A,[expr] direct ADC A,[X+expr] index SUB A,expr data SUB A,[expr] direct SUB A,[X+expr] index SBB ...

Page 19

Absolute Maximum Ratings Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied ...... –0°C to +70°C Supply Voltage on V Relative Input Voltage................................... –0. 8.0 Electrical Characteristics Parameter Description General ...

Page 20

Electrical Characteristics Parameter Description P Port 1 & Cext Sink Mode Dissipation max V Input Threshold Voltage ith V Input Hysteresis Voltage H V Input Hysteresis Voltage, Cext HCext Iin Input Leakage Current, GPIO Pins I Input Leakage Current, ...

Page 21

CLOCK Figure 9-2. USB Data Signal Timing and Voltage Levels T PERIOD Differential Data Lines T PERIOD Differential Data Lines Figure 9-4. Differential to EOP Transition Skew and EOP Width Document #: 38-08026 Rev CYC ...

Page 22

T PERIOD Differential Data Lines 10.0 Ordering Information EPROM Ordering Code Size CY7C63001A-PC 4KB CY7C63001A-PXC 4KB CY7C63001A-SC 4KB CY7C63001A-SXC 4KB CY7C63101A-QC 4KB CY7C63101A-QXC 4KB CY7C63001A-XC 4KB CY7C63001A-XWC 4KB 11.0 Package Diagrams Document #: 38-08026 Rev. *A Crossover Points Consecutive Transitions ...

Page 23

Package Diagrams (continued) Document #: 38-08026 Rev. *A 24-Lead Quarter Size Outline Q13 20-Lead (300-Mil) Molded SOIC S5 CY7C63001A CY7C63101A 51-85055-*B 51-85024-*B Page ...

Page 24

... Document #: 38-08026 Rev. *A © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...

Page 25

Document History Page Document Title: CY7C63001A, CY7C63101A Universal Serial Bus Microcontroller Document Number: 38-08026 REV. ECN NO. Issue Date ** 116223 06/12/02 *A 276070 See ECN Document #: 38-08026 Rev. *A Orig. of Change Description of Change DSG Change from ...

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