MMSF5N03HDR2 ON Semiconductor, MMSF5N03HDR2 Datasheet - Page 6

• Manufacturer Part Number: MMSF5N03HDR2
• Manufacturer: ON Semiconductor

Specifications of MMSF5N03HDR2

• Number Of Elements: 1
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / Rohs Status: Not Compliant

the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
tion temperature and a case temperature (T C ) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance – Gen-
eral Data and Its Use.”
verse any load line provided neither rated peak current (I DM )
nor rated voltage (V DSS ) is exceeded, and that the transition
time (t r , t f ) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(T J(MAX) – T C )/(R JC ).
in switching circuits with unclamped inductive loads. For reli-
MMSF5N03HD
6
The Forward Biased Safe Operating Area curves define
Switching between the off–state and the on–state may tra-
A power MOSFET designated E–FET can be safely used
0.01
100
0.1
10
1
0.1
Figure 12. Maximum Rated Forward Biased
V GS = 10 V
SINGLE PULSE
T C = 25°C
Mounted on 2” sq. FR4 board (1” sq. 2 oz. Cu 0.06”
thick single sided), 10s max.
V DS , DRAIN–TO–SOURCE VOLTAGE (VOLTS)
R DS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
Safe Operating Area
1
dc
10 ms
1 ms
10
di/dt = 300 A/ s
Figure 11. Reverse Recovery Time (t rr )
100 s
SAFE OPERATING AREA
100
t, TIME
able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction tem-
perature.
to–source avalanche at currents up to rated pulsed current
(I DM ), the energy rating is specified at rated continuous cur-
rent (I D ), in accordance with industry custom. The energy rat-
ing must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at cur-
rents below rated continuous I D can safely be assumed to
equal the values indicated.
Although many E–FETs can withstand the stress of drain–
450
300
150
Standard Cell Density
Motorola TMOS Power MOSFET Transistor Device Data
High Cell Density
0
25
t a
Figure 13. Maximum Avalanche Energy versus
t rr
t rr
t b
T J , STARTING JUNCTION TEMPERATURE (°C)
50
Starting Junction Temperature
75
100
125
I D = 15 A
150