AM29F002BT-120EC AMD (ADVANCED MICRO DEVICES), AM29F002BT-120EC Datasheet - Page 13

• Manufacturer Part Number: AM29F002BT-120EC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM29F002BT-120EC

• Lead Free Status / Rohs Status: Not Compliant

Sector protection/unprotection must be implemented
using programming equipment. The procedure
requires a high voltage (V
control pins. Details on this method are provided in the
s u p p l e m e n t s , p u b l i c a t i o n n u m b e r s 2 0 8 1 9
(Am29F002B) and 21183 (Am29F002NB). Contact an
AMD representative to obtain a copy of the appropriate
document.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Temporary Sector Unprotect
Note: This feature requires the RESET# pin and is
therefore not available on the Am29F002NB.
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the
RESET# pin to V
tected sectors can be programmed or erased by
selecting the sector addresses. Once V
from the RESET# pin, all the previously protected
sectors are protected again. Figure 1 shows the algo-
rithm, and the Temporary Sector Unprotect diagram
shows the timing waveforms, for this feature.
November 1, 2006 21527D5
Figure 1. Temporary Sector Unprotect Operation
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
ID
. During this mode, formerly pro-
Program Operations
Completed (Note 2)
Temporary Sector
Perform Erase or
RESET# = V
RESET# = V
ID
Unprotect
(Note 1)
START
) on address pin A9 and the
ID
IH
ID
Am29F002B/Am29F002NB
is removed
D A T A
S H E E T
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi-
nitions table). In addition, the following hardware data
protection measures prevent accidental erasure or pro-
gramming, which might otherwise be caused by
spurious system level signals during V
power-down transitions, or from system noise.
Low V
When V
accept any write cycles. This protects data during V
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
is greater than V
proper signals to the control pins to prevent uninten-
tional writes when V
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
IL
, CE# = V
CC
CC
Write Inhibit
is less than V
IH
or WE# = V
IL
LKO
and OE# = V
CC
. The system must provide the
is greater than V
LKO
IH
. To initiate a write cycle,
, the device does not
IH
during power up, the
CC
LKO
power-up and
.
11
CC
CC