MB15E05SLPV1-G-ER Fujitsu Components, MB15E05SLPV1-G-ER Datasheet - Page 8

• Manufacturer Part Number: MB15E05SLPV1-G-ER
• Manufacturer: Fujitsu Components
• Type: PLL Frequency Synthesizerr

Specifications of MB15E05SLPV1-G-ER

• Number Of Elements: 1
• Supply Current: 3.5mA
• Pll Input Freq (min): 100MHz
• Pll Input Freq (max): 2GHz
• Operating Supply Voltage (typ): 3V
• Operating Temp Range: -40C to 85C
• Package Type: BCC
• Operating Supply Voltage (min): 2.4V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Pin Count: 16
• Lead Free Status / Rohs Status: Not Compliant

8
MB15E05SL
■ FUNCTIONAL DESCRIPTION
1. Pulse Swallow Function
The divide ratio can be calculated using the following equation:
f
2. Serial Data Input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference divider
and the programmable divider separately.
Binary serial data is entered through the Data pin.
One bit of data is shifted into the shift register on the rising edge of the Clock. When the LE signal pin is taken high,
stored data is latched according to the control bit data as follows:
Table 1. Control Bit
(1) Shift Register Configuration
VCO
LSB
CNT
R1 to R14
SW
FC
LDS
CS
Note: Start data input with MSB first.
CNT R1
= [(M × N) + A] × f
1
f
N
A
f
R
M
VCO
OSC
Programmable Reference Counter
Control bit (CNT)
2
: Output frequency of external voltage controlled oscillator (VCO)
: Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
: Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)
: Output frequency of the reference frequency oscillator
: Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
: Preset divide ratio of modulus prescaler (64 or 128)
R2
H
L
: Control bit
: Divide ratio setting bit for the programmable reference counter (3 to 16,383) [Table 2]
: Divide ratio setting bit for the prescaler (64/65 or 128/129)
: Phase control bit for the phase comparator
: LD/f
: Charge pump current select bit
3
R3
OUT
OSC
4
signal select bit
÷ R (A < N)
R4
5
R5
6
For the programmable reference divider
For the programmable divider
R6
7
R7
8
Data Flow
R8
9
R9 R10 R11 R12 R13 R14 SW FC
10
Destination of serial data
11
12
13
14
15
16
[Table 1]
[Table 5]
[Table 8]
[Table 7]
[Table 6]
17
LDS
18
MSB
CS
19