B69000 Asiliant Technologies, B69000 Datasheet - Page 246

• Manufacturer Part Number: B69000
• Manufacturer: Asiliant Technologies

Specifications of B69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

FR36
read/write at I/O address 3D1h with index at I/O address 3D0h set to 36h
7-4
3-0
FR37
read/write at I/O address 3D1h with index at I/O address 3D0h set to 37h
When the FP Display engine is enabled (FR01 bit one is set to 1) it uses this register.
7
6
5-3
2-0
&+,36
FLM Delay
7
7
FP FLM Delay Bits 11-8
See description of FR34.
FP Vertical Total MSB
See description of FR33.
FP VSync (FLM) Delay Disable
This bit is effective when FR37 bit 6 is set to 0.
0: FP VSync (FLM) delay enable
1: FP VSync (FLM) delay disable
FP VSync (FLM) select
0: FP VSync (FLM) is generated using FR37 bit 7 and FP VSync (FLM) Delay (FR36 bits 6-4 and
FR34) .
1: FP VSync (FLM) is the same as CRT VSync. FR37 bit 7 is ignored in this case.
FP Vsync (FLM) width.
These bits are effective only if bit 6 is 0.
Reserved
These bits should always be written to with a value of zero.
69000 Databook
FP Vertical Overflow 2 Register
FP VSync (FLM) Disable Register
FLM Select
FP FLM Delay MSB
6
6
5
5
Subject to Change Without Notice
FP VSync (FLM) width
Flat Panel Registers
Programmed value = actual value -1
4
4
3
3
FP Vertical Total MSB
2
2
Reserved (000)
Revision 1.3 8/31/98
1
1
0
0
15-31