AT49F8192AT-90RC Atmel, AT49F8192AT-90RC Datasheet - Page 3

• Manufacturer Part Number: AT49F8192AT-90RC
• Manufacturer: Atmel

Specifications of AT49F8192AT-90RC

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 20/19Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: SOIC
• Program/erase Volt (typ): 4.5 to 5.5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 1M/512K
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

AT49F008A(T)
Block Diagram
AT49F8192A(T)
Block Diagram
Device
Operation
1199G–FLASH–11/02
READ: The AT49F008A(T)/8192A(T) is accessed like an EPROM. When CE and OE are low
and WE is high, the data stored at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high-impedance state whenever CE or OE
is high. This dual line control gives designers flexibility in preventing bus contention.
COMMAND SEQUENCES: When the device is first powered on, it will be reset to the read or
standby mode, depending upon the state of the control line inputs. In order to perform other
device functions, a series of command sequences are entered into the device. The command
sequences are shown in the Command Definitions table (I/O8 - I/O15 are don’t care inputs for
the command codes). The command sequences are written by applying a low pulse on the
WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the
falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of
CE or WE. Standard microprocessor write timings are used. The address locations used in the
command sequences are not affected by entering the command sequences.
ADDRESS
ADDRESS
INPUTS
INPUTS
RESET
RESET
GND
V CC
GND
V CC
WE
WE
OE
CE
OE
CE
Y DECODER
Y DECODER
X DECODER
X DECODER
CONTROL
CONTROL
LOGIC
LOGIC
DATA INPUTS/OUTPUTS
DATA INPUTS/OUTPUTS
PROGRAM DATA
PROGRAM DATA
INPUT/OUTPUT
INPUT/OUTPUT
MAIN MEMORY
MAIN MEMORY
(496K WORDS)
(992K BYTES)
PARAMETER
PARAMETER
PARAMETER
PARAMETER
BOOT BLOCK
BOOT BLOCK
I/O0 - I/O15
4K WORDS
4K WORDS
I/O0 - I/O7
BUFFERS
LATCHES
Y-GATING
8K BYTES
8K BYTES
16K BYTES
BUFFERS
LATCHES
Y-GATING
8K WORDS
BLOCK 2
BLOCK 1
BLOCK 2
BLOCK 1
AT49F8192A
AT49F008A
AT49F008A(T)/8192A(T)
FFFFF
07FFF
05FFF
03FFF
00000
7FFFF
03FFF
02FFF
01FFF
00000
08000
06000
04000
03000
04000
02000
DATA INPUTS/OUTPUTS
DATA INPUTS/OUTPUTS
PROGRAM DATA
PROGRAM DATA
INPUT/OUTPUT
INPUT/OUTPUT
MAIN MEMORY
MAIN MEMORY
BOOT BLOCK
PARAMETER
PARAMETER
(496K WORDS)
BOOT BLOCK
(992K BYTES)
I/O0 - I/O15
PARAMETER
PARAMETER
I/O0 - I/O7
16K BYTES
4K WORDS
4K WORDS
8K WORDS
BUFFERS
LATCHES
Y-GATING
8K BYTES
8K BYTES
Y-GATING
BUFFERS
LATCHES
BLOCK 1
BLOCK 2
BLOCK 1
BLOCK 2
AT49F8192AT
AT49F008AT
FFFFF
FBFFF
FC000
FA000
F9FFF
F7FFF
00000
F8000
7CFFF
7FFFF
7DFFF
7BFFF
7E000
7D000
7C000
00000
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