AM486DX5-133V16BHC AMD (ADVANCED MICRO DEVICES), AM486DX5-133V16BHC Datasheet - Page 39

• Manufacturer Part Number: AM486DX5-133V16BHC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM486DX5-133V16BHC

• Family Name: Am486
• Device Core Size: 32b
• Frequency (max): 133MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: SQFP
• Lead Free Status / Rohs Status: Not Compliant

6.3
The system interrupts the normal program execution
and invokes SMM by generating a System Management
SMI: System Management Interrupt. This is the trig-
ger mechanism for the SMM interface. When SMI is
asserted (SMI pin asserted Low) it causes the pro-
cessor to invoke SMM. The SMI pin is the only
means of entering SMM.
SMI handler: System Management mode handler.
This is the code that is executed when the processor
is in SMM. Example applications that this code might
implement are a power management control or a
system control function.
RSM: Resume instruction. This instruction is used
by the SMI handler to exit the SMM and return to the
interrupted OS or application process.
SMRAM: This is the physical memory dedicated to
SMM. The SMI handler code and related data reside
in this memory. The processor also uses this mem-
ory to store its context before executing the SMI han-
dler. The operating system and applications should
not have access to this memory space.
SMBASE: This is a control register that contains the
base address that defines the SMRAM space.
Context: This term refers to the processor state. The
SMM discussion refers to the context, or processor
state, just before the processor invokes SMM. The
context normally consists of the CPU registers that
fully represent the processor state.
Context Switch: A context switch is the process of
either saving or restoring the context. The SMM dis-
cussion refers to the context switch as the process
of saving/restoring the context while invoking/exiting
SMM, respectively.
SMSAVE: A mechanism that saves and restores all
internal registers to and from SMRAM.
System Management Interrupt
Processing
Instr
#1
SMIACT
SMI
#2
Instr
SMI
Instr
#3
Enhanced Am486DX Microprocessor Family
Figure 22. Basic SMI Interrupt Service
P R E L I M I N A R Y
State Save
SMI Handler
Interrupt (SMI) to the CPU. The CPU services the SMI
by executing the following sequence (see Figure 22).
1. The CPU asserts the SMIACT signal, instructing the
2. The CPU saves its state (internal register) to SM-
3. The CPU switches to the SMM processor environ-
4. The CPU then jumps to the absolute address of
Note: If the SMRAM shares the same physical address
location with part of the system RAM, it is “overlaid”
SMRAM. To preserve cache consistency and correct
SMM operation in systems using overlaid SMRAM, the
cache must be flushed via the FLUSH pin when entering
SMM.
5. The SMI handler then executes the RSM instruction
For uses such as fast enabling of external I/O devices,
the SMSAVE mode permits the restarting of the I/O in-
structions and the HALT instruction. This is accom-
plished through I/O Trap Restart and Halt/Auto HALT
Restart slots. Only I/O and HALT opcodes are restart-
able. Attempts to restart any other opcode may result
in unpredictable behavior.
The System Management Interrupt hardware interface
consists of the SMI request input and the SMIACT output
used by the system to decode the SMRAM (see Figure
23).
system to enable the SMRAM.
RAM. It starts at the SMBASE relative address lo-
cation (see Section 7.3.3), and proceeds downward
in a stack-like fashion.
ment (an external pseudo-real mode).
SMBASE + 8000h in SMRAM to execute the SMI
handler. This SMI handler performs the system
management activities.
which restores the CPU’s context from SMRAM,
deasserts the SMIACT signal, and then returns con-
trol to the previously interrupted program execution.
RSM
State Restore
#4
Instr
Instr
#5
39