AM28F256-120JC AMD (ADVANCED MICRO DEVICES), AM28F256-120JC Datasheet - Page 13

• Manufacturer Part Number: AM28F256-120JC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM28F256-120JC

• Lead Free Status / Rohs Status: Not Compliant

FLASHERASE ELECTRICAL ERASE ALGORITHM
This Flash memory device erases the entire array in
parallel. The erase time depends on V
and number of erase/program cycles on the device. In
general, reprogramming time increases as the number
of erase/program cycles increases.
The Flasherase electrical erase algorithm employs an
interactive closed loop flow to simultaneously erase all
bits in the array. Erasure begins with a read of the mem-
ory contents. The device is erased when shipped from
the factory. Reading FFh data from the device would
immediately be followed by executing the Flashrite pro-
gramming algorithm with the appropriate data pattern.
Should the device be currently programmed, data other
than FFh will be returned from address locations.
Follow the Flasherase algorithm. Uniform and reliable
erasure is ensured by first programming all bits in the
device to their charged state (Data = 00h). This is
accomplished using the Flashr ite Programming
Notes:
1. See AC and DC Characteristics for values of V
2. Erase Verify is performed only after chip erasure. A final read compare may be performed (optional) after the register is written
3. The erase algorithm Must Be Followed to ensure proper and reliable operation of the device.
Standby
Write
Standby
Write
Standby
Read
Standby
Write
Standby
switchable. When V
with the read command.
Bus Operations
PP
is switched, V
Erase Setup
Erase
Erase-Verify (Note 2)
Reset
Table 4.
PPL
Command
PP
may be ground, no connect with a resistor tied to ground, or less than V
, temperature,
Flasherase Electrical Erase Algorithm
PP
parameters. The V
Am28F256
algorithm. Erasure then continues with an initial erase
operation. Erase verification (Data = FFh) begins at
address 0000h and continues through the array to the
la s t a d d r e s s, o r u n t i l d a t a o t h e r t h a n F F h i s
encountered. If a byte fails to verify, the device is
er as e d ag a in . W i th ea ch er as e o pe r at io n , a n
increasing number of bytes verify to the erased state.
Typically, devices are erased in less than 100 pulses
(one second). Erase efficiency may be improved by
storing the address of the last byte that fails to verify in
a register. Following the next erase operation,
verification may start at the stored address location. A
total of 1000 erase pulses are allowed per reprogram
cycle, which corresponds to approximately 10 seconds
of cumulative erase time. The entire sequence of erase
and byte verification is performed with high voltage
applied to the V
erase algorithm.
Entire memory must = 00h before erasure (Note 3)
Note: Use Flashrite programming algorithm (Figure 3) for
programming.
Wait for V
Initialize:
Addresses
PLSCNT (Pulse count)
Data = 20h
Data = 20h
Duration of Erase Operation (t
Address = Byte to Verify
Data = A0h
Stops Erase Operation
Write Recovery Time before Read = 6 µs
Read byte to verify erasure
Compare output to FFh
Increment pulse count
Data = FFh, reset the register for read operations
Wait for V
PP
power supply can be hard-wired to the device or
PP
PP
Ramp to V
Ramp to V
PP
pin. Figure 1 illustrates the electrical
Comments
PPH
PPL
(Note 1)
(Note 1)
WHWH2
)
CC
+ 2.0 V.
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