SI2107-D-FM Silicon Laboratories Inc, SI2107-D-FM Datasheet
SI2107-D-FM
Specifications of SI2107-D-FM
Related parts for SI2107-D-FM
SI2107-D-FM Summary of contents
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... LNB supply solution. Si2109/10 versions include a hardware channel scan accelerator for fast “blindscan.” The Si2107/08/ 09/10 family features new channel detection and acquisition technology: QuickLock for Si2107/08/09/10 and QuickScan for Si2109/10. QuickLock achieves fast channel acquisition and QuickScan, fast channel detection ...
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... Si2107/08/09/10 2 Rev. 1.0 ...
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... On-Chip LNB DC-DC Step-Up Controller (Si2108/10 Only 6.9. On-Chip Blindscan Controller: QuickScan (Si2109/10 Only 6.10. Sleep Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 9. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 10. Ordering Guide 11. Package Outline: 44-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 12. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 Si2107/08/09/10 Rev. 1.0 Page 3 ...
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... Permanent damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operations sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. The Si2107/08/09/ high-performance RF integrated circuit. Handling and assembly of these devices should only be done at ESD-protected workstations. 4 ...
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... IP3 Min gain L 950 to 2150 MHz LO 100 kHz offset MHz offset N 10 kHz to 1/2 Baud LO Rate At 20 MHz offset t s, Rev. 1.0 Si2107/08/09/10 Min Typ Max Unit — 313 339 mA — 298 335 mA — 400 445 mA — 350 446 mA 2.3 — ...
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... Si2107/08/09/10 Table 5. Receiver Characteristics Parameter Symbol RF Input frequency range Fine tune step size Symbol rate range Carrier offset correction range Carrier lock/acquisition times with QuickLock *Note: For signal with C/N = 8.5 dB Pin = –40 dBm, Channel frequency = 1560 MHz. The code rate has no impact on acquisition time ...
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... Peak LNB supply input current Tone frequency Tone amplitude Tone duty cycle Tone rise and fall time Tone detector frequency capture range Tone detector input amplitude Note: Specifications based on recommended schematics in Figure 8 and Figure 9. Si2107/08/09/10 Symbol Test Condition Min V 10.8 LNB_IN 237 VHIGH = 1101 17 ...
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... Si2107/08/09/10 2 Table Bus Characteristics Parameter SCL clock frequency Bus free time between START and STOP condition Hold time (repeated) START condition. (After this period, the first clock pulse is generated.) LOW period of SCL clock HIGH period of SCL cock Data setup time Data hold time ...
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... Serial mode (TSSCR = 01) Serial mode (TSSCR = 11) Parallel mode Normal operation Data delayed (TSDD = 1) Clock delayed (TSCD = 1) Normal operation Data delayed (TSDD = 1) Clock delayed (TSCD = 1) t cycle t setup t access Rev. 1.0 Si2107/08/09/10 Min Typ Max Unit 11.3 — 28 — 8000 ns 5.1 — 6 ...
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... Si2107/08/09/10 Table 9. MPEG-TS Specifications (Rising Launch, Falling Capture) Parameter Symbol Clock cycle time t cycle Clock low time t clow Clock high time t chigh Hold time t hold Setup time t setup Access time t access L TS_CLK TS_DATA Figure 3. MPEG-TS (Rising Launch, Falling Capture) Timing Diagram ...
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... Input Power (dBm) Figure 4. Eb/No (QEF Operation) vs. Input Power for Si2107/08/09/10 (Typical 27.5 MBaud 7/8 1 0.1 0.01 0.001 0.0001 0.00001 0.000001 0.0000001 0.00000001 2 4 Eb/No (dB) Figure 5. BER After Viterbi vs. Eb/No for Si2107/08/09/10 Si2107/08/09/10 -40 -20 0 27.5Mbaud 1/2 27 ...
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... Si2107/08/09/10 Figure 6. Phase Noise Performance for Si2107/08/09/10 (Typical) 0.3 0.25 0.2 0.15 0.1 0.05 0 -10 Frequency Offset of Desired Channel (MHz) Figure 7. Frequency Offset vs. Carrier Lock/Acquisition Time for Various Baudrates Using QuickLock (Typical) Rev. 1.0 1 Mbaud 2Mbaud 5Mbaud 10Mbaud 20Mbaud 35Mbaud 45Mbaud Test Conditions Pin = – ...
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... XTAL1 1 35 REXT XTAL2 2 34 ADDR VDD_XTAL 3 33 VDD_MIX XTOUT 4 32 VDD_BB VDD_PLL33 5 31 VDD_ADC INT/RLK/GPO 6 30 TDET/VSEN TS_ERR 7 29 TGEN/LNB1 TS_VAL 8 28 NC/ISEN TS_SYNC 9 27 DRC/LNB2 SDA 10 26 RESET SCL 11 25 DCS/PWM TS_DATA7 12 24 VDD_DIG18 TS_DATA6 13 23 Rev. 1.0 Si2107/08/09/10 13 ...
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... Si2107/08/09/10 14 Si2110 LNB Control Si2110 LNB Control Rev. 1.0 ...
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... Si2110 LNB Control Si2110 LNB Control Rev. 1.0 Si2107/08/09/10 15 ...
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... Si2107/08/09/10 3. Bill of Materials Table 10. Si2107/08/09/10 Bill of Materials Component C1,C2,C4,C6,C10,C8,C9,C13,C14, C15,C16 C5 C3,C7,C11,C12 C19,C36 TC1 Notes: 1. Transient voltage suppression device should be selected to match the surge requirements of the application. 2. Tuning component values depend on balun selected and layout. Please contact Silicon Laboratories for assistance reviewing layouts and selecting matching components. ...
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... Q3, R10 R11 R12,R20 R13 R14 R15 R16 R17 Si2107/08/09/10 Description 0.47 µ X7R,± 20 X7R, ± 20% 0.22 µ X7R, ± 20% 4.7 µ X7R, ± 20% CMPSH1- SD0705-330K-R-SL ZXMN3B14 FDN337N FMMT618 MMBT3904 MMBT4401 FMMT718 1.3 Ω, 500 mW, ±5% 33 Ω, 250 mW, ±5% 10 kΩ, 62.5 mW, ±5% 1 kΩ ...
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... Si2107/08/09/10 Table 12. DiSEqC 2.x LNB Supply Bill of Materials (Si2108/10 Only) Component C17 C30 C31,C35 C32 C33 C34 Q3,Q5, R10 R11 R12,R20 R13 R14 R15 R16 R17 R18 18 Description 1200 pF X7R, ± 20% 47 µ Electrolytic, ± 20% 0.47 µ X7R, ± 20 X7R, ± 20% 0.22 µ ...
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... LNB supply regulator circuit. The LNB supply controller utilizes a step-up converter architecture. In case operation with an external regulator is desired, Si2107 and Si2109 can be used; these do not integrate the LNB step-up dc-dc controller. On the other hand, the Si2109 and Si2110 integrate an on-chip “ ...
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... For each valid DVB-S/DSS channel, the tuning frequency and symbol rate, which can be stored by the host for subsequent tuning, are determined. On Si2107/08 devices, the host needs to provide the channel tuning frequency and symbol rate to the device. 5.5. LNB Signaling Controller ...
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... In the continuous mode, the clock runs without regard to data being output, and the user will use TS_VAL as a data strobe. To support board- level timing modifications, the clock stream may be delayed by register bit TSCD. Rev. 1.0 Si2107/08/09/10 Sync/Frame Start Indicator Valid Data Indicator Uncorrectable Packet Error 21 ...
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... Si2107/08/09/10 In serial mode, the transport stream clock rate range is determined by the TSSCR register. The exact rate is determined during the acquisition process. The range that minimizes the difference between the effective transport stream data rate and the clock rate should be chosen. The recommended settings are listed in Table 15 ...
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... TS1 (sync) TS_DATA[0] TS_SYNC, active high TS_VAL, active high TS_ERR, active high TS2 TS188 RS1 TS2 TS188 TS2 TS188 RS1 TS2 TS188 Figure 12. MPEG-TS Parallel Mode Rev. 1.0 Si2107/08/09/10 TS1 (sync) TS2 TS1 (sync) TS2 TS1 (sync) TS2 TS1 (sync) TS2 23 ...
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... Si2107/08/09/10 Continuous Serial Data Mode: TSM = 0, TSCM = 1, TSPG = 0 TS_CLK, rising edge+ TS1 (sync) TS_DATA[0] TS_SYNC, active low 1-bit wide TS_VAL, active low TS_ERR, active low Continuous Serial Data Mode: TSM = 0, TSCM = 1, TSPG = 1 TS_CLK, rising edge+ TS1 (sync) TS_DATA[0] TS_SYNC, active low ...
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... Message received Message parity error Message receive timeout Short-circuit detect Over current detect Si2107/08/09/10 INT can be masked off by using the interrupt enable bit, INT_EN. Note that interrupt reporting in the register map is not affected by INT_EN. The interrupt signal polarity can be configured to be ...
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... Si2107/08/09/10 Table 16. Events, Interrupts, and Status Bits (Continued) Blindscan done Blindscan data ready 26 BSDO_I BSDO_E BSDA_I BSDA_E Rev. 1.0 BSDO BSDA ...
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... Viterbi code rate search (VTF), frame sync search (FSF), and overall receiver acquisition (AQF), 6.4. Tuning Control The Si2107/08/09/10 utilizes a unique two-stage tuning algorithm to provide optimal RF reception. The input signal is first mixed down to a low-IF frequency by a coarse tuning stage and then down to baseband by a fine-tune mixer ...
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... Bandwidth Threshold registers to the QuickLock recommended default values before initiating an acquisition. Refer to Silicon Laboratories Application Note “AN298: Si2107/08/09/10 Programming Interface Example Software" for the recommended default values. The recommended values are documented in the Signal Acquisition section of the application note. When carrier offset estimation is complete, the CEL bit is asserted ...
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... Frame Search lock Unlock Receiver locked Figure 15. Fade Recovery Sequence Si2107/08/09/10 6.4.6. C/N Estimator A carrier-to-noise estimator is provided to aid in satellite antenna positioning. The C/N measurement mode bit, CNM, controls whether the count is performed over a fixed-length or infinite window. With a fixed-length window, the window size is defined by register CNW. ...
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... If an inversion is detected, data are inverted prior to being output. 6.6. Automatic Gain Control The Si2107/08/09/10 is equipped with the ability to adjust signal levels via an automatic gain control (AGC) loop. This ensures that the noise and linearity characteristics of the signal path are optimized at all times ...
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... When gain adjustments are made, the device allows up to 100 µs for the gain changes to settle before beginning the next measurement. To facilitate a rapid initial acquisition, Si2107/08/09/10 includes an acquisition mode wherein the measurement window size is reduced by a factor of 64 when compared to the normal tracking mode. ...
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... Si2107/08/09/10 6.7. LNB Signaling Controller All device versions provide LNB signaling capability. The device supports several LNB signaling methods including dc voltage selection, continuous tone, tone burst, DiSEqC 1.x- and DiSEqC messaging. A description of each method follows. 6.7.1. DC Voltage Selection A constant dc voltage typically used to switch the LNB between horizontal and vertical polarity or clockwise and counterclockwise polarization ...
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... LNB Signaling Modes The LNB signaling modes are described in the following sections. 6.7.4.1. Automatic LNB Messaging Mode The Si2107/08/09/10 LNB Signaling Controller can fully manage the generation and sequencing of all LNB commands. The device is configured in this mode by appropriately programming the LNB Messaging mode register, LNBM ...
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... Si2107/08/09/10 When the tone format select bit, TFS, is programmed to use an external oscillator, the TT bit directly controls the output of the TGEN pin, and the TR bit directly reflects the input of the TDET pin. In this mode, the tone direction control bit, TDIR, directly controls the output of the DRC pin ...
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... The LNB supply circuit resumes normal operation when the connection to the external voltage source has been removed. Si2107/08/09/10 6.9. On-Chip Blindscan Controller: QuickScan (Si2109/10 Only) QuickScan is comprised of a two stage process: a blindscan stage and confirmation stage ...
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... Inband Power Threshold Register. This sets the threshold for determining the drop in power in a detected channel to determine the channel bandwidth. Important highly recommended that the registers in Step 2 be programmed with default values provided by Silicon Laboratories. Refer to “AN298: Si2107/08/09/ 10 Application Programming Interface Software” ...
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... C Control Interface 2 The I C bus interface is provided for configuration and monitoring of all internal registers. The Si2107/08/09/10 supports the 7-bit addressing procedure and is capable of operating at rates up to 400 kbps. Individual data transfers to and from the device are 8-bits. The I data line (SDA). The device always operates as a bus slave. Read and write operations are performed in ...
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... Si2107/08/09/10 8. Control Registers The control registers can be divided into three main classes: Initialization, Run-time, and Status. Initialization registers (“I”) need only be programmed once following device power-up. Run-time registers (“RT”) are the primary registers for device control. Status registers (“S”) provide device state information. The corresponding category of each register is indicated in the rightmost column of Table 19 ...
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... ADCSR[7:0] CTF[7:0] FTF[7:0] FTF[14:8] CFO[7:0] CFO[15:8] CFER[7:0] CFER[15:8] SR[7:0] SR[15:8] SR[23:16] CNET[7:0] CNL[7:0] CNL[15:8] Channel Decoder VTERS VTERC[7:0] VTERC[15:8] RSERS RSERM RSERC[7:0] RSERC[15:8] PRBS_ SYNC Rev. 1.0 Si2107/08/09/ CESR[2:0] CNM CNW[1:0] VTCS[5:0] VTERM VTERW[1:0] VTPS VTIQS RSERW RSERT[1:0] DST_DS DSO_DS PRBS_HEADER_SIZE ...
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... Si2107/08/09/10 Table 19. Register Summary (Continued) Name Addr. AGC Ctrl 1 23h AGC Ctrl 2 24h AGC 1–2 Gain 25h AGC 3–4 Gain 26h AGC TH 27h AGC PL 28h DAGC 1 Ctrl 75h DAGC1_EN DAGC1 L 76h DAGC1 H 77h DAGC2 Ctrl 78h DAGC2 TH 79h DAGC2Lvl L 7Ah DAGC2Lvl H ...
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... D4 D3 QuickScan SR_ CTRL_ HOST SREST[7:0] SREST[15:8] SREST[23:16] SRMAX[7:0] SRMIN[7:0] BSDA BS_FMIN[7:0] BS_FMIN[15:8] BS_FMAX[7:0] BS_FMAX[15:8] BS_CTF[7:0] BS_FTF[7:0] BS_FTF[14:8] BS_ADCSR[7:0] AVG WIN[6:5] SPEC_TILT_CORREC[7:0] BW_1dB[7:0] BW_2dB[7:0] BW_3dB[7:0] INBAND_THRESHOLD[7:0] REF_NOISE_MARGIN[7:0] Rev. 1.0 Si2107/08/09/ ADCSR_ CTF_CTRL_ FTF_CTRL_ CTRL_HOST HOST HOST FALSE_ALA RM_PROC_ EN COESM BS_FMIN[17:16} BS_FMAX[17:16 ...
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... Name 7 Reserved 6 PDE 5 INC_DS 4:3 MOD[1:0] 2:0 SYSM[2: Function Device ID Si2110 1h = Si2109 2h = Si2108 3h = Si2107 Revision. Current revision = INC_DS MOD[1:0] Function Program as shown above. Sleep Mode Disabled (default): normal operation 1 = Enabled Automatic Address Increment Disable Enabled (default Disabled Modulation Selection BPSK demodulation ...
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... Transport Stream Clock Edge Data transitions on rising edge (default Data transitions on falling edge Transport Stream Serial Data Format MSB first (default LSB first Note: This bit is ignored in parallel mode Transport Stream Mode Serial (default Parallel Rev. 1.0 Si2107/08/09/ TSCE TSDF TSM 43 ...
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... Si2107/08/09/10 Register 03h. Transport Stream Control 2 Bit D7 D6 Name 0 Bit Name 7:6 Reserved 5 TSPCS 4 TSCD 3 TSDD 2 TSPG 1:0 TSSCR[1: TSPCS TSCD TSDD Function Program as shown above. Transport Stream Parallel Clock Smoother. Smoothens TS_CLK to ~50% duty cycle Smoothing disabled 1 = Smoothen clock to ~50% duty cycle (default) Transport Stream Clock Delay ...
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... Tri-state (default) Transport Stream Valid Output Enable Enabled 1 = Tri-state (default) Transport Stream Sync Output Enable Enabled 1 = Tri-state (default) Transport Stream Clock Output Enable Enabled 1 = Tri-state (default) Transport Stream Data Output Enable Enabled 1 = Tri-state (default) Rev. 1.0 Si2107/08/09/ TSS_OE TSC_OE TSD_OE Function 45 ...
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... Si2107/08/09/10 Register 05h. Pin Control 2 Bit D7 D6 Name 0 0 Bit Name 7:3 Reserved 2 GPO 1:0 PSEL[1:0] Register 06h. Bypass Bit D7 D6 Name 0 0 Bit Name 7:6 Reserved 5 DS_BP 4 RS_BP 3 DI_BP 2:0 Reserved Function Program as shown above. General Purpose Output Control. Controls output of pin 30 when PSEL = 10 ...
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... Program as shown above. Symbol Timing Lock Interrupt Enable Disabled (default Enabled Carrier Recovery Lock Interrupt Enable Disabled (default Enabled Viterbi Search Lock Interrupt Enable Disabled (default Enabled Frame Sync Lock Interrupt Enable Disabled (default Enabled Rev. 1.0 Si2107/08/09/ CRL_E VTL_E FSL_E 47 ...
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... Si2107/08/09/10 Register 08h. Interrupt Enable 2 Bit D7 D6 Name RCVU_E AGCTS_E Bit Name 7 RCVU_E 6 AGCTS_E 5 STU_E 4 CRU_E 3 VTU_E 2 FSU_E 1 Reserved 0 AQF_E STU_E CRU_E VTU_E FSU_E Function Receiver Unlock Interrupt Enable Disabled (default Enabled AGC Tracking Threshold Interrupt Enable Disabled (default Enabled Symbol Timing Unlock Interrupt Enable. ...
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... Enabled LNB Transmit FIFO Empty Interrupt Enable Disabled (default Enabled LNB Receive FIFO Full Interrupt Enable Disabled (default Enabled LNB Receive Message Interrupt Enable Disabled (default Enabled LNB Receive Timeout Interrupt Enable Disabled (default Enabled Rev. 1.0 Si2107/08/09/ FF_E MSGR_E MSGTO_E 49 ...
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... Bit Name 7 Reserved 6 BSDO_E 5 BSDA_E 4:2 Reserved 1 SCD_E 0 OCD_E Si2107 Si2109/10 BSDA_E0 0 0 Function Program as shown above. Blindscan Done Interrupt Enable Disabled (default Enabled Blindscan Data Ready Interrupt Enable Disabled (default Enabled Program as shown above. Short Circuit Detect Interrupt Enable Disabled (default Enabled Over Current Detect Interrupt Enable ...
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... Carrier Estimator Lock Interrupt Disabled (default Enabled Program as shown above. Symbol Timing Lock Interrupt Disabled (default Enabled Carrier Recovery Lock Interrupt Disabled (default Enabled Viterbi Search Lock Interrupt Disabled (default Enabled Frame Sync Lock Interrupt Disabled (default Enabled Rev. 1.0 Si2107/08/09/ CRL_I VTL_I FSL_I 51 ...
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... Si2107/08/09/10 Register 0Ch. Interrupt Status 2 Bit D7 D6 RCVU_I AGCTS_I Name Bit Name 7 RCVU_I 6 AGCTS_I 5 STU_I 4 CRU_I 3 VTU_I 2 FSU_I 1 Reserved 0 AQF_I STU_I CRU_I VTU_I FSU_I Function Receiver Unlock Interrupt. AGC Tracking Threshold Interrupt Normal operation (default Event recorded Symbol Timing Unlock Interrupt. ...
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... LNB Transmit FIFO Empty Interrupt Normal operation (default Event recorded LNB Receive FIFO Full Interrupt Normal operation (default Event recorded LNB Receive Message Interrupt Normal operation (default Event recorded LNB Receive Timeout Interrupt Normal operation (default Event recorded Rev. 1.0 Si2107/08/09/ FF_I MSGR_I MSGTO_I 53 ...
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... Reserved 6 BSDO_I 5 BSDA_I 4:2 Reserved 1 SCD_I 0 OCD_I Si2107 Si2109/10 BSDA_I 0 0 Function Program to zero. Blindscan Done Interrupt Normal operation (default Blindscan done over the specified frequency range Blindscan Data Ready Interrupt Normal operation (default Blindscan data can be read from registers: BS_CTF, BS_FTF, CFER, SREST, BS_ADCSR. ...
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... Symbol Rate Estimation Status Pending (default Complete Note: Available on Si2109/10 only. Symbol Timing Lock Status Unlocked (default Locked Carrier Lock Status Unlocked (default Locked Viterbi Lock Status Unlocked (default Locked Frame Sync Lock Status Unlocked (default Locked Rev. 1.0 Si2107/08/09/ CRL VTL FSL 55 ...
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... Name RCVL 0 Bit Name 7 RCVL 6:2 Reserved 1 BSDA 0 BSDO Si2107 Si2109/ Function Receiver Lock Status Unlocked (default Locked Program as shown above. Blindscan Data Ready (LSA stage Normal operation (default Raw carrier and symbol rate ready for readout by host. Blindscan Done Normal operation (default Blindscan sequence complete over the specified frequency range ...
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... Note: Available on Si2109/10 only. Symbol Timing Search Status Normal operation (default Search failed Carrier Search Status Normal operation (default Search failed Viterbi Search Status Normal operation (default Search failed Frame Sync Search Status Normal operation (default Search failed Rev. 1.0 Si2107/08/09/ CRF VTF FSF 57 ...
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... Si2107/08/09/10 Register 14h. Acquisition Control 1 Bit D7 D6 Name AQS 0 Bit Name 7 AQS 6:0 Reserved Register 15h. ADC Sampling Rate Bit D7 D6 Name Bit Name 7:0 ADCSR[7:0] Register 16h. Coarse Tune Frequency Bit D7 D6 Name Bit Name 7:0 CTF[7: Function Automatic Acquisition Start. ...
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... Fine Tune Frequency (Low Byte fine where FTF is stored complement value. Calculation of the fine tune value is determined by the reference soft- ware driver. Default: 00h FTF[14:8] Function Program as shown above. Fine Tune Frequency (High Byte). See Register 17h. Rev. 1.0 Si2107/08/09/ × FTF ------- - ...
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... Si2107/08/09/10 Register 1Ch. Host Control Register (Si2109 and Si2110 only) Bit Name Bit Name 7:4 Reserved 3 SR_CTRL_HOST 2 ADCSR_CTRL_HOST 1 CTF_CTRL_HOST 0 FTF_CTRL_HOST Register 23h. Analog AGC Control 1 Bit D7 D6 Name 0 0 Bit Name 7:6 Reserved 5:4 AGCW[1:0] 3:0 Reserved SR_ CTRL_ ADCSR_CTRL_ HOST ...
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... Minimum value for gain stage 4. 0000 = +0 dB (default) 0001 = +1 dB 1110 = +14 dB 1111 = + Function Analog Gain stage 2 setting. Default: 0h Analog Gain stage 1 setting. Default Function Analog Gain stage 4 setting Default: 0h Analog Gain stage 3 setting Default: 0h Rev. 1.0 Si2107/08/09/ AGCO[3: AGC1[3: AGC3[3:0] 61 ...
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... Si2107/08/09/10 Register 27h. AGC Threshold Bit D7 D6 Name 0 Bit Name 7 Reserved 6:0 AGCTH[6:0] Register 28h. AGC Power Level D7 D6 Bit 0 Name Bit Name 7 Reserved 6:0 AGCPWR[6: AGCTH[6:0] Function Program as shown above. Analog AGC Threshold. The value specified in this register corresponds to the desired analog AGC power level ...
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... Symbol Rate Estimate (Low Byte). Result of blindscan symbol rate estimator. Symbol rate = SREST x sampling_rate / 2^23. sampling_rate is the ADC sampling rate as calculated from BS_ADCSR. Default: 00h SREST[15:8] Function Symbol Rate Estimate (Mid Byte). See register 31h. Default: 00h Rev. 1.0 Si2107/08/09/ CESR[2: ...
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... Si2107/08/09/10 Register 33h. Symbol Rate Estimator Register H (Si2109 and Si2110 only) Bit D7 D6 Name Bit Name 7:0 SREST[23:16] Register 36h. Carrier Estimator Offset Bit Name Bit Name 7:0 CFO[7: SREST[23:16] Function Symbol Rate Estimate (High Byte). See register 31h. Default: 00h ...
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... Stores the carrier frequency offset that is identified during the carrier offset estimation stage. Offset = – CFER Note: CFER is a 16-bit two’s complement number. Default: 00h CFER[15:8] Function Carrier Frequency Offset Error (High Byte). See register 38h. Rev. 1.0 Si2107/08/09/ × ------- - ...
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... Si2107/08/09/10 Register 3Ah. Symbol Rate Estimator Control 2 Register Bit Name Bit Name 7:1 Reserved 0 FALSE_ALARM_PROC_EN Register 3Fh. Symbol Rate L Bit D7 D6 Name Bit Name 7:0 SR[7:0] Register 40h. Symbol Rate Bit Name Bit Name 7:0 SR[15: Function Program as shown above. Enable the SRE to check for false symbol rate alarms ...
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... Symbol Rate Estimation Maximum. Max symbol rate Sampling_rate is the ADC sampling rate as calculated from BS_ADCSR. Default: 00h SRMIN[7:0] Function Symbol Rate Estimation Minimum. Min symbol rate Sampling_rate is the ADC sampling rate as calculated from BS_ADCSR. Default: 00h. Rev. 1.0 Si2107/08/09/ × = SRMX ------- - ...
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... Si2107/08/09/10 Register 75h. Digital AGC 1 Control Bit D7 D6 Name 0 DAGC1_EN Bit Name 7 Reserved 6 DAGC1_EN 5:4 DAGC1W[1:0] 3 DAGC1T 2 DAGC1HOLD 1 DAGC1HOST 0 Reserved Register 76h. Digital AGC 1 Gain L Bit D7 D6 Name Bit Name 7:0 DAGC1[7: DAGC1W[1:0] DAGC1T DAGC1HOLD Program as shown above. (Device may change the value of this bit during operation ...
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... Digital AGC2 Automatic Tracking Disable 1 = Disable automatic tracking. Freeze applied to gain Enable automatic tracking. (default DAGC2T[7:0] Function Digital AGC2 Threshold. Default: B5h Rev. 1.0 Si2107/08/09/ DAGC2W[1:0] DAGC2TDIS Tracking 1024 samples (default) 2048 samples 4096 samples 8192 samples ...
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... Si2107/08/09/10 Register 7Ah. Digital AGC 2 Level L Bit D7 D6 Name Bit Name 7:0 DAGC2GA[7:0] Register 7Bh. Digital AGC 2 Level H Bit D7 D6 Name Bit Name 7:0 DAGC2GA[15:8] Register 7Ch. C/N Estimator Control Bit D7 D6 Name CNS 0 Bit Name 7 CNS 6:3 Reserved 2 CNM 1:0 ...
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... This value defines a noise threshold for the C/N estimator. Default: 13h CNL[7:0] Function C/N Estimator Level (Low Byte). The value in this register used with an external lookup table to estimate the C/N of the input signal. Default: 00h CNL[15:8] Function C/N Estimator Level (High Byte). See Register 7Eh. Rev. 1.0 Si2107/08/09/ ...
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... Si2107/08/09/10 Register 80h. QuickScan Control Register Bit D7 D6 BS_START Name 0 Bit Name 7 BS_START 6 Reserved 5 BSDA 4:1 Reserved 0 COESM Register 81h. QuickScan Controller Minimum Frequency Register L (Si2109 and Si2110 only) Bit D7 D6 Name Bit Name 7:0 BS_FMIN[7:0] Lower RF frequency limit for QuickScan range: ...
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... Register 84h. QuickScan Controller Maximum Frequency Register L (Si2109 and Si2110 only) Bit D7 D6 Name Bit Name 7:0 BS_FMAX[7:0] Higher RF frequency limit for QuickScan range: Default: F6h BS_FMIN[15:8] Function Function BS_FMAX[7:0] Function Maximum Frequency (MHz) BS_FMAX ------------------------------------------------------------------------- - = BS_ADCSR (MHz) Rev. 1.0 Si2107/08/09/ BS_FMIN[17:16 × ...
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... Si2107/08/09/10 Register 85h. QuickScan Controller Maximum Frequency Register M (Si2109 and Si2110 only) Bit D7 D6 Name Bit Name 7:0 BS_FMAX[15:8] See register 84h. Default: 9Bh Register 86h. QuickScan Controller Maximum Frequency Register H (Si2109 and Si2110 only) Bit D7 D6 Name 0 0 Bit Name ...
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... Length of the time averaging window for computation for LSA in blind scan mode. Refer to Silicon Laboratories application note AN298 for recommended default val- ues for QuickLock/QuickScan operation. 4:3 Reserved Program as shown above. 2 Reserved Program as shown above. 1:0 Reserved Program as shown above BS_FTF[14:8] Function BS_ADCSR[7:0] Function 02h Function Rev. 1.0 Si2107/08/09/ 01h 02h 75 ...
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... Si2107/08/09/10 Register 8Fh. Spectrum Tilt Correction Threshold Register (Si2109 and Si2110 only) Bit D7 D6 Name Bit Name 7:0 SPEC_TILT_CORREC[7:0] Correction to be applied for spectrum tilt. Register 90h. 1dB Bandwidth Threshold Register (Si2109 and Si2110 only) Bit D7 D6 Name Bit Name 7:0 BW_1dB[7:0] Register 91h ...
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... Bit 5 = 7/8 code rate (MSB) Bit 4 = 6/7 code rate Bit 3 = 5/6 code rate Bit 2 = 3/4 code rate Bit 1 = 2/3 code rate Bit 0 = 1/2 code rate (LSB) Default: All code rates selected (3Fh). Rev. 1.0 Si2107/08/09/ ...
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... Si2107/08/09/10 Register A2h. Viterbi Search Control 2 Bit D7 D6 Name 0 0 Bit Name 7:4 Reserved 3 VTERS 2 VTERM 1:0 VTERW[1:0] Register A3h. Viterbi Search Status Bit D7 D6 VTRS[2:0] Name Bit Name 7:5 VTRS[2:0] 4:2 Reserved 1 VTPS 0 VTIQS VTERS Function Program as shown above. Viterbi BER Measurement Start Writing a one to this bit initiates the Viterbi BER measurement ...
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... Viterbi BER Counter (Low Byte). Stores the number of the Viterbi bit errors detected within the specified measurement window. This register saturates when it reaches the limit of its range. Default: 00h VTERC[15:8] Function Viterbi BER Counter (High Byte). See Register ABh. Rev. 1.0 Si2107/08/09/ ...
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... Si2107/08/09/10 Register B0h. Reed-Solomon BER Error Monitor Control Bit D7 D6 Name 0 0 Bit Name 7:5 Reserved 4 RSERS 3 RSERM 2 RSERW 1:0 RSERT[1:0] Register B1h. Reed-Solomon Error Monitor Count Bit Name Bit Name 7:0 RSERC[7: RSERS RSERM Function Program as shown above. Reed-Solomon BER Measurement Start. ...
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... Bit Name 7:2 Reserved 1 DST_DS 0 DSO_DS RSERC[15:8] Function Reed-Solomon Error Counter (High Byte). See Register B1h Function Program as shown above. Descrambler Transport Error Insertion Disable Enabled (default Disabled Descrambler Inverted SYNC Overwrite Disable Enabled (default Disabled Rev. 1.0 Si2107/08/09/ DST_DS DSO_DS 81 ...
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... Si2107/08/09/10 Register B5h. PRBS Control Bit D7 D6 Name PRBS_START PRBS_INVERT PRBS_SYNC Bit Name 7 PRBS_START 6 PRBS_INVERT 5 PRBS_SYNC 4:2 Reserved 1:0 PRBS_HEADER_SIZE Function Start PRBS Synchronization Start PRBS synchronization Default = 0 Invert PRBS Output PRBS inverted. Default = 0 Synchronization Achieved for PRBS Test Not synchronized. ...
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... Longer than six bytes. Notes: 1. When message length is set to one byte, tone burst modulation is used. When message length is set to two or more bytes, DiSEqC modulation is used. 2. Not available in manual LNB mode Si2107/9 LNBCT LNBB MMSG Si2108/10 LNBCT LNBB MMSG Function Rev. 1.0 Si2107/08/09/ MSGL[2:0] MSGL[2:0] 83 ...
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... Si2107/08/09/10 Register C1h. LNB Control 2 Bit D7 D6 Name LNBM[1:0] Bit Name 7:6 LNBM[1:0] 5:3 Reserved 2 BRST_DS 1 TFS 0 Reserved Register C2h. LNB Control 3 Bit Name TDIR TT TR Bit Name 7 TDIR 4:0 Reserved Function LNB Signaling Mode Automatic (default Step-by-step 10 = Manual 11 = Reserved Program as shown above. ...
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... Bit Name 7 TFQ[7: TFQ[7:0] Function LNB Tone Frequency Control. Used to set the frequency of the LNB tone according to the following equation: Frequency = 100 MHz/[32 x (TFQ+1)] 00000000–01111011 = Reserved 01111100–10011011 = Valid range 10011100–11111111 = Reserved Default: 8Dh = 22 kHz Rev. 1.0 Si2107/08/09/ ...
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... Si2107/08/09/10 Register C4h. LNB Status Bit D7 D6 Name FE FF Bit Name MSGPE 4 MSGR 3 MSGTO 2:0 MSGRL[2: MSGPE MSGR MSGTO Function Message FIFO Empty Normal operation (default Message FIFO empty Message FIFO Full Normal operation (default Message FIFO full Message Parity Error. ...
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... COMP(CEh[2]) register bit. Default: Low voltage = Vlow_nom + 0 Vboost. LNB Supply High Voltage. High voltage = Vhigh_nom + VHIGH[3:0] x 0.0625V + Vboost, where Vhigh_nom is determined by the LNBV(C0h[6]) register bit, and Vboost is determined by the COMP(CEh[2]) register bit. Default: High voltage = Vhigh_nom + 0 Vboost. Rev. 1.0 Si2107/08/09/ VHIGH[3:0] ...
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... Si2107/08/09/10 Register CCh. LNB Supply Control 2 (Si2108 and Si2110 only) Bit D7 D6 Name ILIM[1:0] Bit Name 7:6 ILIM[1:0] 5:4 IMAX[1:0] 3:2 SLOT[1:0] 1:0 OLOT[1:0] Note: This register byte is read-only if LNBL=1. Register CDh. LNB Supply Control 3 (Si2108 and Si2110 only) Bit D7 D6 ...
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... LNB Mode Detect. Detected supply mode (read-only External LNB supply circuit 1 = Internal LNB supply circuit Function Program as shown above. Short-Circuit Detect Flag Normal operation (default Short-circuit detected Overcurrent Detect Flag Normal operation (default Overcurrent detected Rev. 1.0 Si2107/08/09/ COMP 0 LNBMD SCD OCD 89 ...
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... TGEN—Outputs tone or tone envelope. Current Sense (Si2108/10 only). 9 ISEN I Monitors current of LNB supply circuit. When LNB supply circuit is not populated or when using Si2107/09, leave pin unconnected. LNB Control 2/Direction Control. LNB2 (Si2108/10 only)—required connection to LNB supply circuit. 10 LNB2/DRC O DRC—Outputs signal to indicate message transmission (HIGH) or reception (LOW) ...
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... Local oscillator power supply. Connect to 3.3 V. Ground. 38,41,44 GND I Reference ground. RF Input. 39, 43 RFIP1, RFIP2 I These pins must be connected together on the board. RF Input. 40, 42 RFIN1, RFIN2 I These pins must be connected together on the board. Ground. ePad GND I Reference ground. Si2107/08/09/10 Description Rev. 1.0 91 ...
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... Pb-free and RoHS Compliant Si2108-D-FM Satellite receiver for DVB-S/DSS with step-up dc-dc controller, Pb- free and RoHS Compliant Si2107-D-FM Satellite receiver for DVB-S/DSS, Pb-free and RoHS Compliant *Note: Add an “R” at the end of the device to denote tape and reel option; 2500 quantity per reel. 92 Description Rev ...
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... This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VJLD. 3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for small body components. 4. The pin 1 I.D. pad is for component orientation only and is not to be soldered to the PCB. Si2107/08/09/10 Figure 23. 44-Pin QFN Dimension ...
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... Si2107/08/09/10 12. PCB Land Pattern 94 Figure 24. PCB Land Pattern Rev. 1.0 ...
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... A 3x6 array of 0.70mm square openings on 0.95mm pitch should be used for the center ground pad. Notes - Card Assembly No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. Rev. 1.0 Si2107/08/09/10 Min Max 0.50 BSC 7.51 REF 5.51 REF 6.00 6 ...
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... Si2107/08/09/ OTES 96 Rev. 1.0 ...
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... Added graphs of performance illustrating typical performance. Figure 4, “Eb/No (QEF Operation) vs. Input Power for Si2107/08/09/10 (Typical 27.5 MBaud 7/8,” on page 11. Figure 5, “BER After Viterbi vs. Eb/No for Si2107/08/09/ 10,” on page 11. Figure 6, “Phase Noise Performance for Si2107/08/09/ 10 (Typical),” on page 12. Updated “2. Typical Application Schematics”. ...
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... Si2107/08/09/ ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: DBSinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...