MAX515ESA-T Maxim Integrated Products, MAX515ESA-T Datasheet - Page 8

• Manufacturer Part Number: MAX515ESA-T
• Description: DAC (D/A Converters)
• Manufacturer: Maxim Integrated Products

Specifications of MAX515ESA-T

• Number Of Converters: 1
• Resolution: 10 bit
• Interface Type: Serial (3-Wire, SPI, QSPI, Microwire)
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Minimum Operating Temperature: - 40 C
• Dc: 0707
• Lead Free Status / Rohs Status: No

5V, Low-Power, Voltage-Output
Serial 10-Bit DACs
Figure 1. Timing Diagram
8
____________________Pin Description
MAX504
_______________________________________________________________________________________
10
11
12
13
14
1
2
3
4
5
6
7
8
9
DOUT
SCLK
DIN
CS
PIN
MAX515
t
CSH0
—
—
—
—
—
—
1
2
3
4
5
6
7
8
t
DS
REFOUT
BIPOFF
NAME
DGND
AGND
DOUT
REFIN
VOUT
SCLK
CLR
RFB
V
DIN
V
CS
DD
SS
t
CSS
Bipolar offset/gain
resistor
Serial data input
Clear. Asynchronously sets
DAC register to all 0s.
Serial clock input
Chip select, active low
Serial data output for
daisy-chaining
Digital ground
Analog ground
Reference input
Reference output,
2.048V. Connect to V
if not used.
Negative power supply
DAC output
Positive power supply
Feedback resistor
t
DH
t
CH
FUNCTION
t
DO
DD
t
CL
The MAX504/MAX515 use an “inverted” R-2R ladder net-
work with a single-supply CMOS op amp to convert 10-bit
digital data to analog voltage levels (see Functional
Diagram) . The term “inverted” describes the ladder net-
work because the REFIN pin in current-output DACs is the
summing junction, or virtual ground, of an op amp.
However, such use would result in the output voltage
being the inverse of the reference voltage. The
MAX504/MAX515’s topology makes the output the same
polarity as the reference input.
An internal reset circuit forces the DAC register to reset
to all 0s on power-up. Additionally, a clear (CLR) pin,
when held low, sets the DAC register to all 0s. CLR
operates asynchronously and independently from the
chip select (CS) pin.
The output buffer is a unity-gain stable, rail-to-rail output,
BiCMOS op amp. Input offset voltage and CMRR are
trimmed to achieve better than 10-bit performance.
Settling time is 25µs to 0.01% of final value. The output is
short-circuit protected and can drive a 2kΩ load with more
than 100pF load capacitance.
_______________Detailed Description
General DAC Discussion
t
CSH1
t
Buffer Amplifier
CS1
t
CSW