SST39LF020-45-4C-B3K Microchip Technology, SST39LF020-45-4C-B3K Datasheet

SST39LF020-45-4C-B3K

Manufacturer Part Number

SST39LF020-45-4C-B3K

Description

Flash 128K X 8 45ns

Manufacturer

Microchip Technology

Datasheet

1.SST39VF512-70-4C-NHE.pdf (24 pages)

Specifications of SST39LF020-45-4C-B3K

Data Bus Width

8 bit

Memory Type

NOR

Memory Size

2 Mbit

Architecture

Sectored

Interface Type

Parallel

Access Time

45 ns

Supply Voltage (max)

3.6 V

Supply Voltage (min)

3 V

Maximum Operating Current

20 mA

Operating Temperature

+ 70 C

Mounting Style

SMD/SMT

Package / Case

TFBGA-48

Organization

256 KB x 8

Lead Free Status / Rohs Status

Available stocks

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SST39LF020-45-4C-B3K

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SST39LF020-45-4C-B3KE-T

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Microchip Technology

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FEATURES:

• Organized as 64K x8 / 128K x8 / 256K x8 / 512K x8

• Single Voltage Read and Write Operations

• Superior Reliability

• Low Power Consumption

• Sector-Erase Capability

• Fast Read Access Time:

• Latched Address and Data

PRODUCT DESCRIPTION

The SST39LF512, SST39LF010, SST39LF020, SST39LF040

and SST39VF512, SST39VF010, SST39VF020, SST39VF040

are 64K x8, 128K x8, 256K x8 and 5124K x8 CMOS Multi-Pur-

pose Flash (MPF) manufactured with SST’s proprietary, high per-

formance CMOS SuperFlash technology. The split-gate cell

design and thick-oxide tunneling injector attain better reliability and

manufacturability compared with alternate approaches. The

SST39LF512/010/020/040 devices write (Program or Erase) with

a 3.0-3.6V power supply. The SST39VF512/010/020/040 devices

write with a 2.7-3.6V power supply. The devices conform to

JEDEC standard pinouts for x8 memories.

Featuring

SST39LF512/010/020/040 and SST39VF512/010/020/

040 devices provide a maximum Byte-Program time of 20

µsec. These devices use Toggle Bit or Data# Polling to indi-

cate the completion of Program operation. To protect

against inadvertent write, they have on-chip hardware and

Software Data Protection schemes. Designed, manufac-

tured, and tested for a wide spectrum of applications, they

are offered with a guaranteed typical endurance of

100,000 cycles. Data retention is rated at greater than 100

years.

The SST39LF512/010/020/040 and SST39VF512/010/

020/040 devices are suited for applications that require

convenient and economical updating of program, configu-

S71150-14-000

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash

– 3.0-3.6V for SST39LF512/010/020/040

– 2.7-3.6V for SST39VF512/010/020/040

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

(typical values at 14 MHz)

– Active Current: 5 mA (typical)

– Standby Current: 1 µA (typical)

– Uniform 4 KByte sectors

– 45 ns for SST39LF512/010/020/040

– 55 ns for SST39LF020/040

– 70 ns for SST39VF512/010/020/040

high

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39LF/VF512 / 010 / 020 / 0403.0 & 2.7V 512Kb / 1Mb / 2Mb / 4Mb (x8) MPF memories

performance

01/10

Byte-Program,

the

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

• Fast Erase and Byte-Program:

• Automatic Write Timing

• End-of-Write Detection

• CMOS I/O Compatibility

• JEDEC Standard

• Packages Available

• All devices are RoHS compliant

ration, or data memory. For all system applications, they

significantly improves performance and reliability, while low-

ering power consumption. They inherently use less energy

during Erase and Program than alternative flash technolo-

gies. The total energy consumed is a function of the

applied voltage, current, and time of application. Since for

any given voltage range, the SuperFlash technology uses

less current to program and has a shorter erase time, the

total energy consumed during any Erase or Program oper-

ation is less than alternative flash technologies. These

devices also improve flexibility while lowering the cost for

program, data, and configuration storage applications.

The SuperFlash technology provides fixed Erase and Pro-

gram times, independent of the number of Erase/Program

cycles that have occurred. Therefore the system software

or hardware does not have to be modified or de-rated as is

necessary with alternative flash technologies, whose Erase

and Program times increase with accumulated Erase/Pro-

gram cycles.

To meet surface mount requirements, the SST39LF512/

010/020/040 and SST39VF512/010/020/040 devices are

offered in 32-lead PLCC and 32-lead TSOP packages. The

SST39LF/VF010 and SST39LF/VF020 are also offered in

a 48-ball TFBGA package. See Figures 2, 3, 4, and 5 for

pin assignments.

– Sector-Erase Time: 18 ms (typical)

– Chip-Erase Time: 70 ms (typical)

– Byte-Program Time: 14 µs (typical)

– Chip Rewrite Time:

– Internal V

– Toggle Bit

– Data# Polling

– Flash EEPROM Pinouts and command sets

– 32-lead PLCC

– 32-lead TSOP (8mm x 14mm)

– 48-ball TFBGA (6mm x 8mm)

– 34-ball WFBGA (4mm x 6mm) for 1M and 2M

1 second (typical) for SST39LF/VF512

2 seconds (typical) for SST39LF/VF010

4 seconds (typical) for SST39LF/VF020

8 seconds (typical) for SST39LF/VF040

Generation

These specifications are subject to change without notice.

MPF is a trademark of Silicon Storage Technology, Inc.

Data Sheet

Related parts for SST39LF020-45-4C-B3K

SST39LF020-45-4C-B3K Summary of contents

Page 1

... Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 SST39LF/VF512 / 010 / 020 / 0403.0 & 2.7V 512Kb / 1Mb / 2Mb / 4Mb (x8) MPF memories FEATURES: • Organized as 64K x8 / 128K x8 / 256K x8 / 512K x8 • Single Voltage Read and Write Operations – ...

Page 2

... Silicon Storage Technology, Inc. 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit meth- ods ...

Page 3

... Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 Data# Polling ( When the SST39LF512/010/020/040 and SST39VF512/ 010/020/040 are in the internal Program operation, any attempt to read DQ will produce the complement of the 7 true data. Once the Program operation is completed, DQ will produce true data ...

Page 4

... DQ0 DQ0 DQ0 FIGURE 2: Pin Assignments for 32-lead PLCC ©2010 Silicon Storage Technology, Inc. 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 X-Decoder I/O Buffers and Data Latches Control Logic SST39LF/VF512 SST39LF/VF512 32-lead PLCC ...

Page 5

... Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 SST39LF/VF040 SST39LF/VF020 SST39LF/VF010 SST39LF/VF512 A11 A11 A11 A11 A13 A13 A13 A13 A14 A14 A14 A14 A17 A17 NC NC WE# WE# WE# WE A18 A16 A16 A16 NC A15 ...

Page 6

... DD CE# A16 A18 DQ2 V A12 A15 A7 A0 DQ0 NC2 Note: For SST39LF020, ball B3 is "No Connect" For SST39LF010, balls B3 and A5 are "No Connect" -A address lines will select the block 3.0-3.6V for SST39LF512/010/020/040 2.7-3.6V for SST39VF512/010/020/040 for SST39LF/VF020, and A 17 CE# OE# WE OUT ...

Page 7

... Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 TABLE 4: Software Command Sequence Command 1st Bus Sequence Write Cycle 1 Addr Data Byte-Program 5555H AAH Sector-Erase 5555H AAH Chip-Erase 5555H AAH 4,5 Software ID Entry 5555H AAH ...

Page 8

... A sector- or block-level rating would result in a END higher minimum specification. ©2010 Silicon Storage Technology, Inc. 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 = 3.0-3.6V for SST39LF512/010/020/040 and 2.7-3.6V for DD 1 ...

Page 9

... Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 AC CHARACTERISTICS TABLE 9: Read Cycle Timing Parameters - V SST39VF512/010/020/040 Symbol Parameter T Read Cycle Time RC T Chip Enable Access Time CE T Address Access Time AA T Output Enable Access Time ...

Page 10

... SW0 Note Most significant address for SST39LF/VF512 for SST39LF/VF020 and A 17 FIGURE 7: WE# Controlled Program Cycle Timing Diagram ©2010 Silicon Storage Technology, Inc. 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 OLZ T CLZ DATA VALID ...

Page 11

... Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 5555 ADDRESS CPH OE# WE 7-0 SW0 Note Most significant address FIGURE 8: CE# Controlled Program Cycle Timing Diagram ADDRESS A MS-0 CE# OE# WE Note Most significant address for SST39LF/VF512, A ...

Page 12

... Sector Address Most significant address FIGURE 11: WE# Controlled Sector-Erase Timing Diagram ©2010 Silicon Storage Technology, Inc. 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 OEH T OE for SST39LF/VF512, A for SST39LF/VF010, 16 for SST39LF/VF020 and A for SST39LF/VF040 ...

Page 13

... Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 5555 2AAA ADDRESS A MS-0 CE 7-0 SW0 Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchageable as long as minmum timings are met. (See Table 10) ...

Page 14

... V (0 FIGURE 15: AC Input/Output Reference Waveforms TO DUT FIGURE 16: A Test Load Example ©2010 Silicon Storage Technology, Inc. 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 2AAA 5555 IDA T WHP ...

Page 15

... Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 FIGURE 17: Byte-Program Algorithm ©2010 Silicon Storage Technology, Inc. Start Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: A0H Address: 5555H Load Byte ...

Page 16

... Byte-Program/ Erase Initiated Wait SCE Program/Erase Completed FIGURE 18: Wait Options ©2010 Silicon Storage Technology, Inc. 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 Toggle Bit Byte-Program/ Erase Initiated Read byte Read same byte No Does DQ 6 ...

Page 17

... Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 Software ID Entry Command Sequence Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: 90H Address: 5555H Wait T IDA Read Software ID FIGURE 19: Software ID Command Flowcharts © ...

Page 18

... Address: 5555H Wait T SCE Chip erased to FFH FIGURE 20: Erase Command Sequence ©2010 Silicon Storage Technology, Inc. 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 Sector-Erase Command Sequence Load data: AAH Address: 5555H Load data: 55H ...

Page 19

... Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 PRODUCT ORDERING INFORMATION SST 39 LF 040 - XXXX - XXX ©2010 Silicon Storage Technology, Inc XXX X Environmental Attribute E Package Modifier leads balls balls (54 possible positions) Package Type B3 = TFBGA (0.8mm pitch, 6mm x 8mm PLCC M = WFBGA (0 ...

Page 20

... Silicon Storage Technology, Inc. 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 SST39LF010-45-4C-B3KE SST39VF010-70-4C-B3KE SST39VF010-70-4I-B3KE SST39LF020-45-4C-B3KE SST39VF020-70-4C-B3KE SST39VF020-70-4I-B3KE SST39LF040-45-4C-B3KE SST39VF040-70-4C-B3KE SST39VF040-70-4I-B3KE 20 SST39LF010-45-4C-MME SST39LF020-45-4C-MME ...

Page 21

... Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 PACKAGING DIAGRAMS TOP VIEW .495 .485 .453 Optional Pin #1 .447 .048 Identifier .042 .042 .048 .595 .553 .585 .547 .050 BSC Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. ...

Page 22

... Maximum allowable mold flash is 0. the package ends, and 0.25 mm between leads. FIGURE 23: 32-lead Thin Small Outline Package (TSOP) 8mm x 14mm SST Package Code: WH ©2010 Silicon Storage Technology, Inc. 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 8.10 7.90 1.20 max ...

Page 23

... Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 TOP VIEW 6.00 ± 0. CORNER DETAIL SEATING PLANE Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-225, this specific package is not registered. 2. All linear dimensions are in millimeters. ...

Page 24

... Data Sheet TABLE 11: Revision History Number 01 • 2000 Data Book 02 • Changed speed from for the SST39LF020 and SST39LF040 03 • 2002 Data Book: Reintroduced the 45 ns parts for the SST39LF020 and SST39LF040 04 • Added the B3K package for the 2 Mbit devices • ...

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