CY7C09169AV-12AI Cypress Semiconductor Corp, CY7C09169AV-12AI Datasheet - Page 6

• Manufacturer Part Number: CY7C09169AV-12AI
• Description: SRAM Chip Sync Dual 3.3V 144K-Bit 16K x 9-Bit 25ns/12ns 100-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09169AV-12AI

• Package: 100TQFP
• Timing Type: Synchronous
• Density: 144 Kb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 3.3 V
• Address Bus Width: 14 Bit
• Number Of I/o Lines: 9 Bit
• Number Of Ports: 2
• Number Of Words: 16K

Document #: 38-06053 Rev. *B
Switching Characteristics
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
MAX1
MAX2
CYC1
CYC2
CH1
CL1
CH2
CL2
R
F
SA
HA
SC
HC
SW
HW
SD
HD
SAD
HAD
SCN
HCN
SRST
HRST
OE
OLZ
OHZ
CD1
CD2
DC
CKHZ
CKLZ
CWDD
CCS
Port to Port Delays
Parameter
f
f
Clock Cycle Time - Flow-Through
Clock Cycle Time - Pipelined
Clock HIGH Time - Flow-Through
Clock LOW Time - Flow-Through
Clock HIGH Time - Pipelined
Clock LOW Time - Pipelined
Clock Rise Time
Clock Fall Time
Address Set-up Time
Address Hold Time
Chip Enable Set-up Time
Chip Enable Hold Time
R/W Set-up Time
R/W Hold Time
Input Data Set-up Time
Input Data Hold Time
ADS Set-up Time
ADS Hold Time
CNTEN Set-up Time
CNTEN Hold Time
CNTRST Set-up Time
CNTRST Hold Time
Output Enable to Data Valid
OE to Low Z
OE to High Z
Clock to Data Valid - Flow-Through
Clock to Data Valid - Pipelined
Data Output Hold After Clock HIGH
Clock HIGH to Output High Z
Clock HIGH to Output Low Z
Write Port Clock High to Read Data Delay
Clock to Clock Set-up Time
Max
Max
Flow-Through
Pipelined
Over the Operating Range
Description
Min.
25
15
12
12
6
6
4
1
4
1
4
1
4
1
4
1
4
1
4
1
2
1
2
2
2
-9
Max.
CY7C09159AV
40
67
10
20
40
15
3
3
7
9
9
Min.
30
20
12
12
8
8
4
1
4
1
4
1
4
1
4
1
4
1
4
1
2
1
2
2
2
-12
CY7C09159AV
CY7C09169AV
Max.
33
50
12
25
12
40
15
3
3
7
9
Page 6 of 16
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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