CY7C1347D-250AC Cypress Semiconductor Corp, CY7C1347D-250AC Datasheet
CY7C1347D-250AC
Specifications of CY7C1347D-250AC
Related parts for CY7C1347D-250AC
CY7C1347D-250AC Summary of contents
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... CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1347D SRAM integrate 131,072 x 36 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK) ...
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... Functional Block Diagram—CY7C1347D BWa# BWE# CLK BWb# GW# BWc# BWd# CE# CE2 CE2# OE# ZZ Power Down Logic ADSP ADSC# ADV# A1-A0 MODE Note: 1. The functional block diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information. ...
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... V 11 CCQ DQc 12 DQc DQd 18 DQd CCQ DQd 22 DQd 23 DQd 24 DQd CCQ DQd 28 DQd 29 DQd 30 Document #: 38-05022 Rev. *D 100-Pin TQFP Top View CY7C1347D CY7C1347D DQb 80 DQb 79 78 DQb 77 V CCQ DQb DQb 74 DQb 73 72 DQb CCQ DQb 69 DQb DQa 63 DQa CCQ ...
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... DQc E DQc F V CCQ G DQc H DQc J V CCQ K DQd L DQd M V CCQ N DQd P DQd CCQ CY7C1347D Pin Descriptions BGA Pins QFP Pins 2A, 3A, 5A, 6A, 35, 34, 33, 32, 3B, 5B, 2C, 3C, 100, 99, 82, 81, 5C, 6C, 2R, 6R, 44, 45, 46, 47, 3T, 4T, 5T 48, 49 Document #: 38-05022 Rev. *D 119-Ball BGA ...
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... CY7C1347D Pin Descriptions BGA Pins QFP Pins 1B, 7B, 1C, 7C, 4D, 14, 16, 66 3J, 5J, 4L, 1R, 5R, 7R, 1T, 2T, 6T, 6U Burst Address Table (MODE = NC/V First Second Third Address Address Address (external) (internal) (internal) A...A00 A...A01 A...A10 A...A01 A...A00 A...A11 A...A10 A...A11 A...A00 A...A11 A...A10 A ...
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... Each of the TAPs registers are serial shift registers that capture serial input data on the rising edge of TCK and push serial data out on subsequent falling edge of TCK. When a register is selected connected between the TDI and TDO pins. CY7C1347D ADSC ADV Write OE ...
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... TAP controller’s capture setup plus hold time (t device clock input(s) need not be paused for any other TAP operation except capturing the input and I/O ring contents into the boundary scan register. CY7C1347D plus t ). The CS CH ...
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... Reserved Do not use these instructions. They are reserved for future use. 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- Figure 1. TAP Controller State Diagram CY7C1347D 1 SELECT IR-SCAN 0 1 CAPTURE-IR 0 SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- [8] Page ...
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... CCQ 0V < V < < V < Output disabled, 0V < V < CCQ [10, 12] = 100 µA I OLC [10, 12] = 100 µA I OHC /2, Undershoot: V (AC)<–0.5V for t<t /2, Power-up KHKH CY7C1347D 0 Selection Circuitry [9] Min. Max. 2.0 4.6 1.7 4.6 2 0.3 CCQ 1 0.3 CCQ –0.5 0.8 –0.3 0.7 – ...
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... V = Min 3 CCQ = 8 Min 2.5V CCQ = 2 Min 2.5V CCQ = 1.0 mA [10 Min 3 CCQ = –4 Min 2.5V, CC CCQ I = –2 [13, 14] Over the Operating Range Description CY7C1347D Min. Max. 0.4 OLT 0.7 OLT 0.4 OLT 2.4 OH 2.0 Min. Max Page Unit Unit ns MHz ns ...
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... Reserved for revision number. 00111 Defines depth of words. 00011 Defines width of bits. XXXXXX Reserved for future use. 00011100100 Allows unique identification of DEVICE vendor. 1 Indicates the presence register. Bit Size (x36 CY7C1347D ALL INPUT PULSES 3.3V / 2.5V 1.5V 1 TLTH Description Page ...
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... Description Boundary Scan Order Bump ID Bit CY7C1347D (continued) Signal Name TQFP Bump ID ADSP 84 ADSC 64F BWE CLK BWa 93 BWb 94 5G BWc 95 3G BWd 100 DQc 1 DQc 2 DQc 3 DQc 6 1G DQc 7 DQc 8 DQc 9 DQc 12 2G DQc DQd 18 DQd 19 DQd 22 2M DQd 23 Page ...
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... Boundary Scan Order (continued) Bit# Signal Name TQFP 59 DQd 60 DQd 61 DQd 62 DQd 63 DQd 64 MODE Document #: 38-05022 Rev. *D Bump CY7C1347D Page ...
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... Device deselected; all inputs < > all inputs static Max.; CLK frequency = 0 CC Device deselected; all inputs < > Max.; CLK cycle time > t min CY7C1347D Ambient [15] Temperature 3.3V −5%/+10% 0°C to +70°C Min. Max. 2.0 4.6 1.7 4.6 2 0.3 CCQ 1 ...
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... KQHZ KQLZ OEHZ CY7C1347D Typ. Max TQFP Typ. BGA Typ ALL INPUT PULSES 90% 90% 10% 0V ≤ 1.5 ns (c) 200 MHz 166 MHz Max ...
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... Document #: 38-05022 Rev. *D Output Low Voltage I (mA) Max. OH –105 –105 –105 –83 –70 –30 – OEQ OELZ Q(A1) Q(A2) Q(A2+1) SINGLE READ CY7C1347D Pull-Down Current V (V) I (mA) Min –0 0.4 10 0.8 20 1.25 31 1.6 40 2.8 40 3.2 40 3.4 40 Q(A2+2) Q(A2+3) Q(A2) BURST READ (mA) Max ...
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... Switching Waveforms (continued) [26, 27] Write Timing CLK t S ADSP# ADSC ADDRESS A1 BWa#, BWb#, BWc#, BWd#, BWE#, GW# GW# CE# ADV# OE# t KQX DQ Q Document #: 38-05022 Rev OEHZ D(A1) D(A2) D(A2+1) D(A2+1) SINGLE WRITE BURST WRITE CY7C1347D D(A2+2) D(A2+3) D(A3) D(A3+1) BURST WRITE D(A3+2) Page ...
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... CLK t S ADSP# ADSC ADDRESS A2 BWa#, BWb#, BWc#, BWd#, BWE#, GW# CE# ADV# OE# DQ Ordering Information Speed (MHz) Ordering Code 250 CY7C1347D-250AC CY7C1347D-250BGC 225 CY7C1347D-225BGC 200 CY7C1347D-200AC 166 CY7C1347D-166AC Document #: 38-05022 Rev Q(A1) Q(A2) D(A3) Single Reads Single Write Package Name A101 100-Lead ...
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... Package Diagrams 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 Document #: 38-05022 Rev. *D CY7C1347D 51-85050-*A Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 119-Lead FBGA ( 2.4 mm) BG119 CY7C1347D 51-85115-*B Page ...
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... Document History Page Document Title: CY7C1347D: 128K x 36 Synchronous-Pipelined Cache SRAM Document Number: 38-05022 Orig. of Rev. ECN No. Issue Date Change ** 106740 05/07/01 *A 107485 06/06/01 *B 121064 11/13/02 *C 122474 01/18/03 *D 212291 See ECN Document #: 38-05022 Rev. *D RCS New Data Sheet RCS Added Minimum and Maximum values for 2.5V V and all other subsequent parameters ...