A1460A-1PQ208C Actel, A1460A-1PQ208C Datasheet

A1460A-1PQ208C

Manufacturer Part Number

A1460A-1PQ208C

Description

FPGA ACT 3 Family 6K Gates 848 Cells 125MHz 0.8um (CMOS) Technology 5V 208-Pin PQFP

Manufacturer

Actel

Datasheet

1.A1460A-1PQ208C.pdf (68 pages)

Specifications of A1460A-1PQ208C

Package

208PQFP

Family Name

ACT 3

Device Logic Gates

6000

Device Logic Units

848

Device System Gates

15000

Number Of Registers

768

Maximum Internal Frequency

125 MHz

Typical Operating Supply Voltage

5 V

Maximum Number Of User I/os

167

Maximum Propagation Delay Time

2.6 ns

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

A1460A-1PQ208C

Manufacturer:

NSC

Quantity:

306

Company:

BOSTOCK HK LIMITED

Part Number:

A1460A-1PQ208C

Manufacturer:

Microsemi SoC

Quantity:

10 000

Current page: 1 of 68
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Accelerator Series FPGAs

– ACT

F e a t u re s

• Up to 10,000 Gate Array Equivalent Gates

• Highly Predictable Performance with 100% Automatic

• 7.5 ns Clock-to-Output Times

• Up to 250 MHz On-Chip Performance

• Up to 228 User-Programmable I/O Pins

• Four Fast, Low-Skew Clock Networks

• More than 500 Macro Functions

S ep te mb er 199 7

Device

Capacity

Logic Modules

Dedicated Flip-Flops

User I/Os (maximum)

Packages

Performance

Notes:

Gate Array Equivalent Gates

PLD Equivalent Gates

TTL Equivalent Packages (40 gates)

20-Pin PAL Equivalent Packages (100 gates)

S-Module

C-Module

CPGA

PLCC

PQFP

RQFP

VQFP

TQFP

BGA

CQFP

Chip-to-Chip

Accumulators (16-bit)

Loadable Counter (16-bit)

Prescaled Loadable Counters (16-bit)

Datapath, Shift Registers

Clock-to-Output (pad-to-pad)

(up to 25,000 equivalent PLD Gates)

Placement and Routing

One flip-flop per S-Module, two flip-flops per I/O-Module.

See product plan on page 1-178 for package availability.

Based on A1415A-3, A1425A-3, A1440B-3, A1460B-3, and A14100B-3.

Clock-to-Output + Setup

(by pin count)

(maximum, worst-case commercial)

™

3 Family

108 MHz

110 MHz

250 MHz

63 MHz

A1415

7.5 ns

1,500

3,750

200

104

264

100

—

• Replaces up to twenty 32 macro-cell CPLDs

• Replaces up to one hundred 20-pin PAL

• Up to 1153 Dedicated Flip-Flops

• VQFP, TQFP, BGA, and PQFP Packages

• Nonvolatile, User Programmable

• Fully Tested Prior to Shipment

• 5.0V and 3.3V Versions

• Optimized for Logic Synthesis Methodologies

• Low-power CMOS Technology

108 MHz

110 MHz

250 MHz

100, 160

63 MHz

A1425

7.5 ns

2,500

6,250

310

160

150

360

100

133

100

132

—

100 MHz

110 MHz

250 MHz

63 MHz

10,000

A1440

8.5 ns

4,000

100

564

288

276

568

140

175

160

100

176

—

110 MHz

200 MHz

160, 208

97 MHz

63 MHz

15,000

A1460

9.0 ns

6,000

150

848

432

416

768

207

176

225

196

168

—

Packages

105 MHz

200 MHz

A14100

93 MHz

63 MHz

10,000

25,000

9.5 ns

1,377

1,153

1-175

250

100

697

680

228

257

208

313

256

—

Related parts for A1460A-1PQ208C

A1460A-1PQ208C Summary of contents

Page 1

... Based on A1415A-3, A1425A-3, A1440B-3, A1460B-3, and A14100B-3. 4. Clock-to-Output + Setup 199 7 © 1997 Actel Corporation • Replaces up to twenty 32 macro-cell CPLDs • Replaces up to one hundred 20-pin PAL • 1153 Dedicated Flip-Flops • VQFP, TQFP, BGA, and PQFP Packages • Nonvolatile, User Programmable • ...

Page 2

... Chip #1 I/O Module I/O CLK t CKHS A1425A-3 7.5 A1460A-3 9.0 1-176 The ACT 3 family is supported by Actel’s Designer Series Development System which offers automatic placement and routing (with automatic or fixed pin assignments), static timing anlaysis, user programming, and debug and diagnostic probe capabilities. The Designer Series is supported on the following platforms: 486/Pentium class PC’ ...

Page 3

... Die Revision Part Number A1415A = 1500 Gates A14V15A = 1500 Gates (3.3V) A1425A = 2500 Gates A14V25A = 2500 Gates (3.3V) A1440A = 4000 Gates A14V40A = 4000 Gates (3.3V) A1460A = 6000 Gates A14V60A = 6000 Gates (3.3V) A14100A = 10000 Gates A14V100A = 10000 Gates (3.3V – 208 C ...

Page 4

... Plastic Leaded Chip Carrier (PLCC) 100-pin Very Thin Quad Flatpack (VQFP) 160-pin Plastic Quad Flatpack (PQFP) 176-pin Thin Quad Flatpack (TQFP) A1460A Device 160-pin Plastic Quad Flatpack (PQFP) 176-pin Thin Quad Flatpack (TQFP) 196-pin Ceramic Quad Flatpack (CQFP) 207-pin Ceramic Pin Grid Array (CPGA) ...

Page 5

Pro duc t Plan (continued) A14V60A Device 160-pin Plastic Quad Flatpack (PQFP) 176-pin Thin Quad Flatpack (TQFP) 208-pin Plastic Quad Flatpack (PQFP) A14100A Device 208-pin Power Quad Flatpack (RQFP) 257-pin Ceramic Pin Grid Array (CPGA) 313-pin Plastic Ball Grid Array ...

Page 6

Hermetic D evice R eso ur ces Device Logic Series Modules Gates A1415 200 1500 A1425 310 2500 A1440 564 4000 A1460 848 6000 A14100 1377 10000 Pin Descrip tion CLKA Clock A (Input) Clock input for clock distribution networks. ...

Page 7

Arch itec ture This section of the data sheet is meant to familiarize the user with the architecture of the ACT 3 family of FPGA devices. A generic description of the family will be presented first, followed by a detailed ...

Page 8

The S-module contains a full implementation of the C-module plus a clearable sequential element that can either implement a latch or flip-flop function. The S-module can therefore implement any function implemented by the C-module. This allows complex combinatorial-sequential functions to ...

Page 9

D ODE MUX Figure 4 • Functional Diagram for I/O Module I/O Pad Drivers All pad drivers are capable of being tristate. Each buffer connects to an associated I/O module with four signals: OE (Output Enable), IE ...

Page 10

OE SLEW DATAOUT DATAIN IEN INEN OUTEN Figure 5 • Function Diagram for I/O Pad Driver Routed Clocks The routed clock networks are referred to as CLK0 and CLK1. Each network is connected to a clock module (CLKMOD) that selects ...

Page 11

Each output segment spans four channels (two above and two below), except near the top and bottom of the array where edge effects occur. LVTs contain either one or two TRACK SEGMENT HF Figure 7 • Horizontal Routing Tracks ...

Page 12

Antifuse Connections An antifuse is a “normally open” structure as opposed to the normally closed fuse structure used in PROMs or PALs. The use of antifuses to implement a programmable logic device results in highly testable structures as well as ...

Page 13

B1 B0 D01 D00 A1 D10 D11 A0 S-MODULES Figure 9 • Logic Module Routing Interface A cceler ator Se rie s FP GAs – Y+2 Y+2 Y+1 Y+1 Y Y-1 Y-2 LVTs ™ 3 Fami ly B0 ...

Page 14

... Supply Current (typical = 0.7 mA) CC( Dynamic V Supply Current See “Power Dissipation” Section CC(D) CC Notes: 1. Actel devices can drive and receive either CMOS or TTL signal levels. No assignment of I/Os as TTL or CMOS is required. 2. Tested one output at a time min Not tested, for information only 0V MHz. ...

Page 15

Operating C ond ons A bso lu te Maxi Free air temperature range Symbol Parameter V DC Supply Voltage –0 Input Voltage –0 ...

Page 16

... Static Power Component * Actel FPGAs have small static power components that result lower power dissipation than PALs or PLDs. By integrating (1) multiple PALs/PLDs into one FPGA, an even greater reduction in board-level power dissipation can be achieved. The power due to standby current is typically a small component of the overall power. Standby power is calculated below for commercial, worst case conditions ...

Page 17

... Measurements have been made over a range of frequencies at a fixed value of V capacitance is frequency independent so that the results may be used over a wide range of operating conditions. Equivalent capacitance values are shown below. C Values for Actel FPGAs EQ Modules (C ) EQM Input Buffers ( ) ...

Page 18

... A1415A 104 A14V15A 104 A1425A 160 A14V25A 160 A1440A 288 A14V40A 288 A1440B 288 A1460A 432 A14V60A 432 A1460B 432 A14100A 697 A14V100A 697 A14100B 697 1-192 Determining Average Switching Frequency To determine the switching frequency for a design, you must r ...

Page 19

Timi ng M ode l * Input Delays I/O Module t = 2.8 ns INY t IRD2 0.0 ns INH t = 1.8 ns INSU t = 4.7 ns ICKY ARRAY CLOCK t ...

Page 20

Output B uffe r Del ays GND 50% 50 1.5 V Out 1 DHS, DHS, AC Test Loa ds Load 1 (Used to measure propagation delay) To the output under ...

Page 21

Sequ ential Modu Cha tics Flip-Flops D t SUD CLK Q CLR I /O Mod ule: S eque Inp ut Tim in g Charact ...

Page 22

dule: Sequent put acter is tics D t OUTSU IOCLK PRE, CLR 1-196 D PRE E IOCLK CLR Y (Positive edge triggered) t OUTH ...

Page 23

... FPGA. This tight distribution is achieved in two ways: by decreasing the delay of the interconnect elements and by decreasing the number of interconnect elements per path. Actel’s patented PLICE antifuse offers a very low resistive/capacitive interconnect. The ACT 3 family’s antifuses, fabricated in 0.8 micron m lithography, offer nominal levels of 200 resistance and 6 femtofarad (fF) capacitance per antifuse ...

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