XC3S500E-4FG320C Xilinx Inc, XC3S500E-4FG320C Datasheet - Page 94

• Manufacturer Part Number: XC3S500E-4FG320C
• Description: FPGA Spartan-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 320-Pin FBGA
• Manufacturer: Xilinx Inc

Specifications of XC3S500E-4FG320C

• Package: 320FBGA
• Family Name: Spartan-3E
• Device Logic Cells: 10476
• Device Logic Units: 1164
• Device System Gates: 500000
• Number Of Registers: 9312
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 232
• Ram Bits: 368640

Functional Description
After the FPGA configures itself using BPI mode from one
end of the parallel Flash PROM, then the FPGA can trigger
a MultiBoot event and reconfigure itself from the opposite
end of the parallel Flash PROM. MultiBoot is only available
when using BPI mode and only for applications with a single
Spartan-3E FPGA.
By default, MultiBoot mode is disabled. To trigger a Multi-
Boot event, assert a Low pulse lasting at least 300 ns on the
MultiBoot Trigger (MBT) input to the STARTUP_SPARTAN3E
library primitive. When the MBT signal returns High after the
300 ns or longer pulse, the FPGA automatically reconfig-
ures from the opposite end of the parallel Flash memory.
Figure 60
loads itself from the attached parallel Flash PROM. In this
In another potential application, the initial design loaded into
the FPGA image contains a “golden” or “fail-safe” configura-
tion image, which then communicates with the outside world
and checks for a newer image. If there is a new configura-
tion revision and the new image verifies as good, the
“golden” configuration triggers a MultiBoot event to load the
new image.
When a MultiBoot event is triggered, the FPGA then again
drives its configuration pins as described in
94
First Configuration
Parallel Flash PROM
shows an example usage. At power up, the FPGA
Di agnostics
Application
Application
User Area
General
FPGA
FPGA
Figure 60: Use MultiBoot to Load Alternate Configuration Images
FFFFFF
0
> 300 ns
Table
59. How-
STARTUP_SPARTAN3E
GSR
GTS
MBT
CLK
www.xilinx.com
example, the M0 mode pin is Low so the FPGA starts at
address 0 and increments through the Flash PROM mem-
ory locations. After the FPGA completes configuration, the
application initially loaded into the FPGA performs a
board-level or system test using FPGA logic. If the test is
successful, the FPGA then triggers a MultiBoot event, caus-
ing the FPGA to reconfigure from the opposite end of the
Flash PROM memory. This second configuration contains
the FPGA application for normal operation.
Similarly, the general FPGA application could trigger
another MultiBoot event at any time to reload the diagnos-
tics design, and so on.
ever, the FPGA does not assert the PROG_B pin. The sys-
tem design must ensure that no other device drives on
these same pins during the reconfiguration process. The
FPGA’s DONE, LDC[2:0], or HDC pins can temporarily dis-
able any conflicting drivers during reconfiguration.
Asserting the PROG_B pin Low overrides the MultiBoot fea-
ture and forces the FPGA to reconfigure starting from the
end of memory defined by the mode pins, shown in
Table
58.
Reconfigure
Second Configuration
P arallel Flash PROM
DS312-2 (v3.8) August 26, 2009
Di agnostics
Application
Application
User Area
General
FPGA
FPGA
Product Specification
DS312-2_51_103105
FFFFFF
0
R