A3961SLB Allegro, A3961SLB Datasheet - Page 5

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A3961SLB

Manufacturer Part Number
A3961SLB
Description
Dual Full Bridge PWM Motor Driver 24-Pin SOIC W
Manufacturer
Allegro
Type
Dual Full Bridge PWM Motor Driverr
Datasheet

Specifications of A3961SLB

Package
24SOIC W
Maximum Operating Current
85 mA
Operating Temperature
-20 to 85 °C

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
A3961SLB
Manufacturer:
SANYO
Quantity:
150
Part Number:
A3961SLB
Manufacturer:
ALLEGRO/雅丽高
Quantity:
20 000
Internal PWM Current Control. The A3961S— contains
a fixed off-time pulse-width modulated (PWM) current-
control circuit that can be used to limit the load current to
a desired value. The peak value of the current limiting
(I
resistor (R
The internal circuitry compares the voltage across the
external sense resistor to the voltage on the reference
input terminal (V
function approximated by:
resistor divider from V
can be switched from a nominal value of 2.5 V to 1.67 V
by applying a low or high logic signal respectively to the
I
voltage reference, the resistor divider (R
have an impedance of 3 k to 15 k . Within this range, a
low impedance will minimize the effect of the REF IN input
offset current.
follows: when the load current reaches I
tor resets a latch that turns off the selected source driver.
The load inductance causes the current to recirculate
through the sink driver and flyback diode.
(R
(t
abled (see “RC Fixed Off-time” below). The range of rec-
ommended values for C
1500 pF and 15 k to 100 k respectively. For optimal
load current regulation, C
“Load Current Regulation” below). At the end of the RC in-
terval, the source driver is enabled allowing the load cur-
rent to increase again. The PWM cycle repeats, maintain-
ing the peak load current at the desired value.
RC BLANKING. In addition to determining the fixed off-
time of the PWM control circuit, the C
comparator blanking time. This function blanks the output
of the comparator when the outputs are switched by the
TRIP
FULL/PD
OFF
3961
DUAL FULL-BRIDGE
PWM MOTOR DRIVER
T
) and capacitor (C
The reference input voltage is typically set with a
The current-control circuitry limits the load current as
For each bridge, the user selects an external resistor
) is set by the selection of an external current-sensing
= R
terminal. To ensure proper operation of the
T
C
S
FUNCTIONAL DESCRIPTION
T
) and reference input voltage (V
) during which the source driver remains dis-
REF IN
I
TRIP
T
), resulting in a transconductance
REF OUT
) to determine the time period
T
T
and R
V
R
is normally set to 1000 pF (see
REF IN
S
. The value of V
T
are 1000 pF to
T
component sets the
TRIP
D
= R
REF IN
, the compara-
REF OUT
1
I
+R
AVG
).
2
) should
[(V
BB
- V
SAT(SOURCE+SINK)
internal current-control circuitry (or by the PHASE or
ENABLE inputs). The comparator output is blanked to
prevent false over-current detections due to reverse-
recovery currents of the clamp diodes, and/or switching
transients related to distributed capacitance in the load.
time, the comparator’s output is blanked and C
be charged from approximately 1.1 volts by an internal
current source of approximately 1 mA. The comparator
output remains blanked until the voltage on C
approximately 3.0 volts.
is discharged to near ground during the crossover delay
time (The crossover delay time is present to prevent
simultaneous conduction of the source and sink drivers).
After the crossover delay, C
rent source of approximately 1 mA. The comparator out-
put remains blanked until the voltage on C
approximately 3.0 volts.
C
re-enabled, C
of approximately 1 mA. The comparator output remains
blanked until the voltage on C
3.0 volts.
1000 pF. This value ensures that the blanking time is suffi-
cient to avoid false trips of the comparator under normal
operating conditions. For optimal regulation of the load
current, the above value for C
value of R
mation regarding load current regulation, see below.
Load Current Regulation. Because the device operates
in a slow decay mode (2-quadrant PWM mode), there is a
limit to the lowest level that the PWM current control cir-
cuitry can regulate load current. The limitation is due to the
minimum PWM duty cycle, which is a function of the user-
selected value of t
t
If the motor is not rotating, as in the case of a stepper mo-
tor in hold/detent mode, a brush dc motor when stalled or
at startup, the worst case value of current regulation can
be approximated by:
ON(min)
T
is discharged to near ground. When the device is
During internal PWM operation, at the end of the t
When a transition of the PHASE input occurs, C
When the device is disabled, via the ENABLE input,
The minimum recommended value for C
max that occurs each time the PWM latch is reset.
1.05 (t
T
can be sized to determine t
T
is charged by an internal current source
) t
ON(min)
ON(min)
OFF
max + t
and the minimum on-time pulse
max] – (1.05 (V
T
is charged by an internal cur-
OFF
T
T
reaches approximately
is recommended and the
) R
LOAD
OFF
SAT(SINK)
. For more infor-
T
reaches
T
T
reaches
T
+ V
begins to
is
F
) t
T
OFF
OFF
)

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