LFE2-20SE-5FN256I Lattice, LFE2-20SE-5FN256I Datasheet - Page 130

• Manufacturer Part Number: LFE2-20SE-5FN256I
• Description: IC FPGA 21KLUTS 256FPBGA
• Manufacturer: Lattice

Specifications of LFE2-20SE-5FN256I

• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 208 PQFP (Cont.)
Number
* Supports true LVDS. Other differential signals must be emulated with external resistors.
** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.
Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the
last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one
connection with a package ball or pin.
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
Pin
Function
VCCAUX
VCCIO0
VCCIO0
Pin/Pad
PT28A
PT26B
PT26A
PT20B
PT20A
PT18B
PT18A
PT16B
PT16A
PT12B
PT12A
PT8B
PT8A
PT6B
PT6A
PT2B
PT2A
GND
GND
GND
VCC
VCC
Bank
LFE2-12E/SE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
-
-
PCLKT0_0
Function
VREF2_0
VREF1_0
Dual
Differential
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
4-30
Function
VCCAUX
VCCIO0
VCCIO0
Pin/Pad
PT37A
PT36B
PT36A
PT30B
PT30A
PT26B
PT26A
PT20B
PT20A
PT12B
PT12A
PT8B
PT8A
PT6B
PT6A
PT2B
PT2A
GND
GND
GND
VCC
VCC
LatticeECP2/M Family Data Sheet
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
-
-
LFE2-20E/SE
PCLKT0_0
Function
VREF2_0
VREF1_0
Dual
Pinout Information
Differential
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T