AD8108AST Analog Devices Inc, AD8108AST Datasheet

IC VIDEO CROSSPOINT SWIT 80LQFP

AD8108AST

Manufacturer Part Number
AD8108AST
Description
IC VIDEO CROSSPOINT SWIT 80LQFP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD8108AST

Rohs Status
RoHS non-compliant
Function
Video Crosspoint Switch
Circuit
1 x 8:8
Voltage Supply Source
Dual Supply
Voltage - Supply, Single/dual (±)
±4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
80-LQFP
Array Configuration
8x8
Number Of Arrays
1
Screening Level
Industrial
Pin Count
80
Package Type
LQFP
Power Supply Requirement
Dual
Lead Free Status / RoHS Status
Not Compliant

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EATURES
8 × 8 high speed nonblocking switch arrays
Serial or parallel programming of switch array
Serial data out allows daisy-chaining of multiple 8 × 8 arrays
Output disable allows connection of multiple devices
Pin-compatible with AD8110/AD8111 16 × 8 switch arrays
For 16 × 16 arrays see AD8116
Complete solution
Excellent video performance
Excellent ac performance
Low power of 45 mA
Low all hostile crosstalk of −83 dB @ 5 MHz
Reset pin allows disabling of all outputs (connected through
Excellent ESD rating: exceeds 4000 V human body model
80-lead LQFP (12 mm × 12 mm)
APPLICATIONS
Routing of high speed signals including
GENERAL DESCRIPTION
The AD8108/AD8109 are high speed 8 × 8 video crosspoint
switch matrices. They offer a −3 dB signal bandwidth greater than
250 MHz and channel switch times of less than 25 ns with 1%
settling. With −83 dB of crosstalk and −98 dB isolation (@5 MHz),
the AD8108/AD8109 are useful in many high speed applications.
The differential gain and differential phase of better than 0.02%
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
AD8108: G = 1
AD8109: G = 2
to create larger switch arrays
Buffered inputs
Eight output amplifiers
Drives 150 Ω loads
60 MHz 0.1 dB gain flatness
0.02%/0.02° differential gain/differential phase error
−3 dB bandwidth: 325 MHz (AD8108), 250 MHz (AD8109)
Slew rate: 400 V/μs (AD8108), 480 V/μs (AD8109)
a capacitor to ground provides power-on reset capability)
Composite video (NTSC, PAL, S, SECAM)
Component video (YUV, RGB)
Compressed video (MPEG, Wavelet)
3-level digital video (HDB3)
AD8108 (G = 1)
AD8109 (G = 2)
(R
L
= 150 Ω)
8 INPUTS
and 0.02°, respectively, along with 0.1 dB flatness out to 60 MHz,
make the AD8108/AD8109 ideal for video signal switching.
The AD8108 and AD8109 include eight independent output
buffers that can be placed into a high impedance state for paral-
leling crosspoint outputs so that off channels do not load the
output bus. The AD8108 has a gain of 1, while the AD8109
offers a gain of 2. They operate on voltage supplies of ±5 V
while consuming only 45 mA of idle current. The channel
switching is performed via a serial digital control (which can
accommodate daisy-chaining of several devices) or via a parallel
control allowing updating of an individual output without
re-programming the entire array.
The AD8108/AD8109 is packaged in an 80-lead LQFP package
and is available over the extended industrial temperature range
of −40°C to +85°C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
UPDATE
DATA IN
325 MHz, 8 × 8 Buffered Video
RESET
CLK
CE
AD8108/AD8109
FUNCTIONAL BLOCK DIAGRAM
Figure 1. Functional Block Diagram
SER/PAR D0 D1 D2 D3
© 2005 Analog Devices, Inc. All rights reserved.
8  4:8 DECODERS
PARALLEL LATCH
Crosspoint Switches
32-BIT SHIFT REGISTER
PARALLEL LOADING
DECODE
SWITCH
MATRIX
WITH 4-BIT
32
32
64
AD8108/AD8109
OUTPUT
BUFFER
G = +1
G = +2
SET INDIVIDUAL
OR RESET ALL
OUTPUTS
TO "OFF"
8
www.analog.com
A0
A1
A2
DATA
OUT
8 OUTPUTS

Related parts for AD8108AST

AD8108AST Summary of contents

Page 1

EATURES 8 × 8 high speed nonblocking switch arrays AD8108 AD8109 Serial or parallel programming of switch array Serial data out allows daisy-chaining of multiple 8 × 8 arrays to create larger switch arrays ...

Page 2

AD8108/AD8109 TABLE OF CONTENTS AD8108/AD8109—Specifications ................................................. 3 Timing Characteristics (Serial) .................................................. 5 Timing Characteristics (Parallel) ............................................... 6 Absolute Maximum Ratings............................................................ 8 Maximum Power Dissipation ..................................................... 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Typical Performance Characteristics ........................................... 11 ...

Page 3

AD8108/AD8109—SPECIFICATIONS V = ± +25° kΩ, unless otherwise noted Table 1. Parameter Conditions DYNAMIC PERFORMANCE −3 dB Bandwidth 200 mV p- p-p, R Propagation Delay 2 V p-p, ...

Page 4

AD8108/AD8109 Parameter INPUT CHARACTERISTICS Input Offset Voltage Input Voltage Range Input Capacitance Input Resistance Input Bias Current SWITCHING CHARACTERISTICS Enable On Time Switching Time Step Switching Transient (Glitch) POWER SUPPLIES Supply Current Supply Voltage Range PSRR OPERATING TEMPERATURE ...

Page 5

TIMING CHARACTERISTICS (SERIAL) Table 2. Timing Characteristics Parameter Serial Data Setup Time CLK Pulse Width Serial Data Hold Time CLK Pulse Separation, Serial Mode CLK to UPDATE Delay UPDATE Pulse Width CLK to DATA OUT Valid, Serial Mode Propagation Delay, ...

Page 6

AD8108/AD8109 TIMING CHARACTERISTICS (PARALLEL) Table 4. Timing Characteristics Parameter Data Setup Time CLK Pulse Width Data Hold Time CLK Pulse Separation CLK to UPDATE Delay UPDATE Pulse Width Propagation Delay, UPDATE to Switch On or Off CLK, UPDATE Rise and ...

Page 7

Table 6. Operation Truth Table UPDATE CE CLK DATA IN DATA OUT Data Data … D3 parallel f A0 … A2 mode X… ...

Page 8

AD8108/AD8109 ABSOLUTE MAXIMUM RATINGS Table 7. Parameter Supply Voltage 1 Internal Power Dissipation AD8108/AD8109 80-Lead Plastic LQFP (ST) Input Voltage Output Short-Circuit Duration 2 Storage Temperature Range 1 Specification is for device in free air (T = 25°C): A 80-lead ...

Page 9

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IN00 1 AGND 2 IN01 3 AGND 4 IN02 5 AGND 6 IN03 7 AGND 8 IN04 9 AGND 10 IN05 11 AGND 12 IN06 13 AGND 14 IN07 15 AGND 16 AVEE 17 AVCC ...

Page 10

AD8108/AD8109 Table 8. Pin Function Descriptions Pin No. Mnemonic 11, 13, 15 INxx 57 DATA IN 58 CLK 59 DATA OUT 56 UPDATE 61 RESET SER/PAR 41, 38, 35, 32, 29, 26, ...

Page 11

TYPICAL PERFORMANCE CHARACTERISTICS 150Ω FLATNESS 1 0 GAIN –1 2V p-p –2 –3 100k 1M 10M FREQUENCY (Hz) Figure 7. AD8108 Frequency Response – 1kΩ L –20 –30 –40 –50 ALL ...

Page 12

AD8108/AD8109 p-p 2 FLATNESS 1 0 GAIN –1 –2 2V p-p –3 100k 1M 10M FREQUENCY (Hz) Figure 13. AD8109 Frequency Response – 1kΩ L –30 –40 –50 –60 –70 ADJACENT –80 –90 –100 ...

Page 13

R = 150Ω L –40 –50 –60 –70 –80 –90 10k 100k 1M FREQUENCY (Hz) Figure 19. AD8108 PSRR vs. Frequency 100 56.3 31.6 17.8 10 5.63 3.16 10 100 1k 10k 100k FREQUENCY (Hz) Figure 20. AD8108 Voltage ...

Page 14

AD8108/AD8109 – 150Ω L –40 –50 –60 –70 –80 –90 10k 100k FREQUENCY (Hz) Figure 25. AD8109 PSRR vs. Frequency 100.0 56.3 31.6 17.8 10.0 5.63 3.16 10 100 1k 10k FREQUENCY (Hz) Figure 26. AD8109 Voltage Noise ...

Page 15

FREQUENCY (Hz) Figure 31. AD8108 Input Impedance vs. Frequency V = 200mV 150Ω –2 –4 –6 –8 30k 100k 1M 10M 100M ...

Page 16

AD8108/AD8109 1M 100k 10k 1k 100 100k 1M 10M 30k FREQUENCY (Hz) Figure 37. AD8109 Input Impedance vs. Frequency V = 100mV 150 Ω –2 –4 –6 –8 30k 100k 1M ...

Page 17

I/O SCHEMATICS V CC ESD INPUT ESD AVEE Figure 43. Analog Input V CC ESD OUTPUT 1kΩ ESD (AD8109 ONLY) AVEE Figure 44. Analog Output V CC ESD 20kΩ ESD DGND Figure 45. Reset Input ESD INPUT ESD Figure 46. ...

Page 18

AD8108/AD8109 THEORY OF OPERATION The AD8108 ( and AD8109 ( share a common core architecture consisting of an array of 64 transconductance (gm) input stages organized as eight 8:1 multiplexers with a common 8-line analog input ...

Page 19

AD8108/AD8109. When taken low, the RESET signal will only set each output to the disabled state. This is helpful during power-up to ensure that two parallel outputs will not be active at the same time. After initial power-up, the internal ...

Page 20

AD8108/AD8109 CREATING LARGER CROSSPOINT ARRAYS The AD8108/AD8109 are high density building blocks for creating crosspoint arrays of dimensions larger than 8 × 8. Various features, such as output disable, chip enable, and gain-of-1 and-2 options, are useful for creating larger ...

Page 21

Using additional crosspoint devices in the design can lower the number of outputs that must be wire-OR’ together. Figure 51 shows a block diagram of a system using eight AD8108s and two AD8109s to create a nonblocking, gain-of-2, ...

Page 22

AD8108/AD8109 CROSSTALK Many systems, such as broadcast video, that handle numerous analog signal channels have strict requirements for keeping the various signals from influencing any of the others in the system. Crosstalk is the term used to describe the coupling ...

Page 23

If a larger crosspoint array of multiple AD8108/AD8109s is constructed, the numbers grow larger still. Obviously, some subset of all these cases must be selected to be used as a guide for a practical measure ...

Page 24

AD8108/AD8109 PCB LAYOUT Extreme care must be exercised to minimize additional crosstalk generated by the system circuit board(s). The areas that must be carefully detailed are grounding, shielding, signal routing, and supply bypassing. The packaging of the AD8108/AD8109 is designed ...

Page 25

Figure 53. Component Side Silkscreen Figure 54. Board Layout (Component Side) Rev Page AD8108/AD8109 ...

Page 26

AD8108/AD8109 Figure 55. Board Layout (Signal Layer) Figure 56. Board Layout (Power Plane) Rev Page ...

Page 27

Figure 57. Board Layout (Bottom Layer) Rev Page AD8108/AD8109 ...

Page 28

AD8108/AD8109 EVALUATION BOARD A 4-layer evaluation board for the AD8108/AD8109 is available. The exact same board and external components are used for each device. The only difference is the device itself, which offers a selection of a gain of unity ...

Page 29

DVCC DGND NC AVEE AGND AVCC NC P1-1 P1-2 P1-3 P1-4 P1-5 P1-6 P1 CR1 CR2 1N4148 + 0.1µF 10µF 0.1µF 10µF 0.1µF 10µF 1 INPUT 00 INPUT 00 2 AGND 75Ω 3 INPUT 01 INPUT 01 4 ...

Page 30

... VIEW A ROTATED 90° CCW 1 ORDERING GUIDE Model Temperature Range AD8108AST −40°C to +85°C 2 AD8108ASTZ −40°C to +85°C AD8109AST −40°C to +85°C 2 AD8109ASTZ −40°C to +85°C AD8108-EB AD8109-EB 1 Details of the lead finish composition can be found on the ADI website Pb-free part ...

Page 31

NOTES Rev Page AD8108/AD8109 ...

Page 32

AD8108/AD8109 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C01068–0–9/05(B) Rev Page ...

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