C8051T605-GSR Silicon Laboratories Inc, C8051T605-GSR Datasheet - Page 93

• Manufacturer Part Number: C8051T605-GSR
• Description: MCU 8-Bit C8051T60x 8051 CISC 2KB EPROM 1.8V/3V 14-Pin SOIC T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051T605-GSR

• Package: 14SOIC
• Device Core: 8051
• Family Name: C8051T60x
• Maximum Speed: 25 MHz
• Ram Size: 256 Byte
• Program Memory Size: 2 KB
• Operating Supply Voltage: 1.8|3 V
• Data Bus Width: 8 Bit
• Program Memory Type: EPROM
• Number Of Programmable I/os: 8
• Interface Type: I2C/SMBus/UART
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

19.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V
V
increases (V
power-on and V
cause the device to be released from reset before V
1 ms, the power-on reset delay (T
On exit from a power-on or V
When PORSF is set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is
cleared by all other resets). Since all resets cause program execution to begin at the same location
(0x0000) software can read the PORSF flag to determine if a power-up was the cause of reset. The con-
tent of internal data memory should be assumed to be undefined after a power-on reset. The V
is disabled following a power-on reset.
Logic HIGH
RST
Logic LOW
. A delay occurs before the device is released from reset; the delay decreases as the V
DD
DD
ramp time is defined as how fast V
RST
Figure 19.2. Power-On and V
monitor event timing. The maximum V
V
RST
DD
monitor reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1.
Power-On
PORDelay
Reset
T
) is typically less than 0.3 ms.
PORDelay
Rev. 1.2
DD
DD
DD
reaches the V
ramps from 0 V to V
DD
C8051T600/1/2/3/4/5/6
Monitor Reset Timing
ramp time is 1 ms; slower ramp times may
RST
Monitor
Reset
VDD
level. For ramp times less than
RST
). Figure 19.2. plots the
DD
settles above
DD
VDD
DD
ramp time
monitor
t
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