DS21372T+ Maxim Integrated Products, DS21372T+ Datasheet - Page 5

• Manufacturer Part Number: DS21372T+
• Description: IC TESTER BIT ERROR 3.3V 32-TQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21372T+

• Function: Bit Error Rate Tester (BERT)
• Interface: T1
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 10mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• Includes: Error Counter, Pattern Generator and Detector
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

DS21372 REGISTER MAP Table 2
NOTE:
1. The Test Register must be set to 00 hex to insure proper operation of the DS21372.
PIN
ADDRESS R/W
24
25
26
27
28
29
30
31
32
0A
0B
00
01
02
03
04
05
06
07
08
09
SYMBOL
RDATA
TDATA
RCLK
TCLK
RDIS
TDIS
V
V
RL
DD
SS
R/W Pattern Set Register 3.
R/W Pattern Set Register 2.
R/W Pattern Set Register 1.
R/W Pattern Set Register 0.
R/W Pattern Length Register.
R/W Polynomial Tap Register.
R/W Pattern Control Register.
R/W Error Insert Register.
R
R
R
R
TYPE DESCRIPTION
Bit Counter Register 3.
Bit Counter Register 2.
Bit Counter Register 1.
Bit Counter Register 0.
O
I
I
I
I
-
-
I
I
REGISTER NAME
Receive Load. A positive-going edge loads the previous 32 bits of data
received at RDATA into the Pattern Receive Registers. RL is logically
OR’ed with control bit PCR.3. Should be tied to V
Receive Data. Received NRZ serial data, sampled on the rising edge of
RCLK.
Receive Disable. Set high to prevent the data at RDATA from being
sampled. Set low to allow bits at RDATA to be sampled. Should be tied
to V
operations are disabled when RDIS is high.
Receive Clock. Input clock from transmission link. 0 to 20 MHz. Can
be a gapped clock. Fully independent from TCLK.
Positive Supply. 3.3V.
Signal Ground. 0.0V. Should be tied to local ground plane.
Transmit Clock. Transmit demand clock. 0 to 20 MHz. Can be a
gapped clock. Fully independent of RCLK.
Transmit Disable. Set high to hold the current bit being transmitted at
TDATA. Set low to allow the next bit to appear at TDATA. Should be
tied to V
side operations are disabled when TDIS is high.
Transmit Data. Transmit NRZ serial data, updated on the rising edge of
TCLK.
SS
if not used. See Figure 6 for timing information. All receive side
SS
if not used. See Figure 7 for timing information. All transmit
ADDRESS R/W
5 of 22
0D
0C
1C
0E
0F
10
11
12
13
14
15
R/W Interrupt Mask Register.
R/W Test Register (see note 1)
R
R
R
R
R
R
R
R
R
Bit Error Counter Register 3.
Bit Error Counter Register 2.
Bit Error Counter Register 1.
Bit Error Counter Register 0.
Pattern Receive Register 3.
Pattern Receive Register 2.
Pattern Receive Register 1.
Pattern Receive Register 0.
Status Register.
REGISTER NAME
SS
if not used.
DS21372