DS2155LN+ Maxim Integrated Products, DS2155LN+ Datasheet - Page 126

• Manufacturer Part Number: DS2155LN+
• Description: IC TXRX T1/E1/J1 1-CHIP 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS2155LN+

• Function: Single-Chip Transceiver
• Interface: E1, HDLC, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 75mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: BERT Generator and Detector, CMI Coder and Decoder, HDLC Controller
• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 64 Kbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 75 mA (Typ)
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DS2155
23.
HDLC CONTROLLERS
This device has two enhanced HDLC controllers, HDLC #1 and HDLC #2. Each controller is
configurable for use with time slots, Sa4 to Sa8 bits (E1 mode), or the FDL (T1 mode). Each HDLC
controller has 128-byte buffers in the transmit and receive paths. When used with time slots, the user can
select any time slot or multiple time slots, contiguous or noncontiguous, as well as any specific bits
within the time slot(s) to assign to the HDLC controllers.
The user must not map both transmit HDLC controllers to the same Sa bits, time slots or, in T1 mode,
map both controllers to the FDL. HDLC #1 and HDLC #2 are identical in operation and therefore the
following operational description refers only to a singular controller.
The HDLC controller performs the entire necessary overhead for generating and receiving performance
report messages (PRMs) as described in ANSI T1.403 and the messages as described in AT&T TR54016.
The HDLC controller automatically generates and detects flags, generates and checks the CRC check
sum, generates and detects abort sequences, stuffs and destuffs zeros, and byte aligns to the data stream.
The 128-byte buffers in the HDLC controller are large enough to allow a full PRM to be received or
transmitted without host intervention.
23.1 Basic Operation Details
The HDLC registers are divided into four groups: control/configuration, status/information, mapping, and
FIFOs.
Table 23-A
lists these registers by group.
23.2 HDLC Configuration
The HxTC and HxRC registers perform the basic configuration of the HDLC controllers. Operating
features such as CRC generation, zero stuffer, transmit and receive HDLC mapping options, and idle
flags are selected here. These registers also reset the HDLC controllers.
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