IA3222B-F-FTR Silicon Laboratories Inc, IA3222B-F-FTR Datasheet
IA3222B-F-FTR
Specifications of IA3222B-F-FTR
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IA3222B-F-FTR Summary of contents
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... PACKAGE OPTIONS 1 16 LineStat ICT Hook 1 V SCLK 2 15 ICT ICR ICR ICG ICG HCap 5 OUT REF 10-pin MSOP (IA3222B OUT EXT 1 ExtClk EXT 2 16-pin QSOP (IA3223) Hook 1 LineStat 1 20 ICT ICT 2 V SCLK ICR 3 CS ICR ICG 8-pin SOIC (IA3222A) ...
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... Pulse Dialing ................................................................................................................................................................................6 Caller ID .......................................................................................................................................................................................6 Power-Down Mode.......................................................................................................................................................................6 PACKAGE PIN DEFINITIONS.....................................................................................................................................................7 IA3223 System Side (QSOP-16) ..................................................................................................................................................7 IA3223A System Side (QSOP-20) ...............................................................................................................................................8 IA3222A Line Side (SOIC-8) ........................................................................................................................................................9 IA3222B Line Side (MSOP-10) ....................................................................................................................................................9 ELECTRICAL SPECIFICATIONS..............................................................................................................................................10 Absolute Maximum Ratings........................................................................................................................................................10 Recommended Operating Conditions ........................................................................................................................................10 DC Characteristics .....................................................................................................................................................................11 AC Characteristics......................................................................................................................................................................11 Off-Hook Receiver Performance ................................................................................................................................................12 On-Hook Receiver (Caller ID) Performance at 48V Transmitter Performance ...
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Line Reversal .............................................................................................................................................................................31 Line Activity ................................................................................................................................................................................31 Line in Use and Line Disconnect ................................................................................................................................................32 The LineStat Pin as Interrupt (On Hook) ....................................................................................................................................32 Audio Snooping..........................................................................................................................................................................32 Theory of Operation— Off-Hook Line Status..............................................................................................................................32 Line Drop....................................................................................................................................................................................33 Parallel Pickup ...........................................................................................................................................................................33 The LineStat Pin as Interrupt (Off ...
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TABLE OF FIGURES Figure 1: Serial interface write-cycle timing diagram (Data output pin floating)................................................................................. 10 Figure 2: Serial interface read-cycle timing diagram............................................................................................................................ 11 Figure 3: Transmit gain with resistive loads.......................................................................................................................................... 15 Figure 4: Transmit gain with complex loads.......................................................................................................................................... 15 Figure ...
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OVERVIEW The chipset provides integrated solution, a low-cost worldwide compliant telephone line interface. Due to its high level of integration, only a few external components are required for operation. Its patented IsoBridge eliminates the need for costly and ...
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AC Termination (Line Impedance Matching) The chipset offers several different AC impedance terminations selectable through the serial port. These AC impedances can be combined with any DC termination selected to address a country’s loop or trunk interface requirements. Refer to ...
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PACKAGE PIN DEFINITIONS Pin-type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output PU=weak internal pull-up resistor PD=weak internal pull-down resistor IA3223 System Side Pin Definitions Pin Number Pin Name 1 LineStat 2 SCLK 3 CS OUT ...
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IA3223 System Side Pin Definitions Pin Number Pin Name 1 LineStat 2 SCLK 3 CS OUT OUT 8 ExtClk 9 RNG/PPU 10 LIU/ OfHk 13 C EXT2 ...
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... HCap Holding capacitor connection 6 Receiver path sensing capacitor input GND Device ground 8 Device supply, self regulated through hook-switch transistor V DD IA3222B Line Side Pin Definitions Pin Number Pin Name Pin Function 1 Hook Hook-switch control 2 ICT Line-Side IsoBridge 3 ICR Line-Side IsoBridge 4 ICG ...
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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Parameter Junction operating and storage temperature ESD (human body model) Power-supply voltage Voltage at any pin Current at any input or output (System Side) Loop Current (IA3222) Recommended Operating Conditions Symbol Parameter Operating temperature Vdd ...
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DC Characteristics Parameter Conditions Logic input current Logic input hysteresis Logic output low voltage I = -4mA OL Logic output high voltage I = 4mA OH RTH[1: RTH[1: Ring-detection threshold RTH[1: RTH[1: ...
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Off-Hook Receiver Performance Parameter Idle channel noise referred to Tip and Ring Total harmonic distortion Gain from Tip and Ring to RX pin OUT Gain from Tip and Ring to RX pin OUT Receiver power headroom Maximum level at RX ...
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Transmitter Performance Parameter Idle channel noise referred to Tip and Ring Total harmonic distortion Gain from TX pin to Tip and Ring IN Part-to-part gain variation at 1kHz, 600 Ω mode, normal headroom Transmitter power headroom, sine wave (See note.) ...
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Line-Side Characteristics Parameter Self-regulated supply voltage Current protection threshold On-hook voltage-protection threshold Temperature-shutdown threshold On-hook DC resistance, Tip to Ring Ringer equivalent load Return loss at 1 kHz (typical) or 300 – 3400 Hz (minimum) Echo return loss, ITU-T G.122 ...
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TYPICAL PERFORMANCE GRAPHS Transmit gain with resistive loads versus frequency (Hz 500 1000 1500 2000 600 Ω, LP[5:4]=00 600 Ω, LP[5:4]=01 Figure 3: Transmit gain with resistive loads Transmit gain at high ...
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Snoop gain versus DC voltage (V) 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0 Low gain High gain Figure 9: Snoop gain versus line DC voltage DC voltage drop (V) versus loop current (mA) 13 ...
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Hybrid loss (dB) with resistive loads versus frequency (Hz 500 1000 1500 2000 2500 600 Ω, LP[5:4]=00 900 Ω, LP[5:4]=01 Figure 15: Trans-hybrid ...
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Receiver-path PSR aliasing into audio band with selected out-of-band frequencies Receiver-path PSR aliasing into audio band with selected out-of-band frequencies -44 -46 -48 -50 -52 -54 -56 -58 -60 -62 -64 -66 -68 -70 -72 10 100 1000 Frequency (kHz) ...
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... Device powered down (Note) (Note) Cx required? IA3222A IA3222B (IA3222B only) Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes IA3222/IA3223 D0 PWD LP2 REVID RTH0 LP F0 Reserved Reset state Low High Low Low Cx1 required? (IA3222B only) Yes Yes Yes 19 ...
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Threshold Register LTH1 LTH0 Line-in-Use Threshold (VDC 22.5 ±7.5 V (reset state ±10V ± Line-disconnect detection (~2.5 V) Note: The parallel-pickup threshold must be selected based on line usage and ...
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Divider Register Clock Mode Internal (reset state External divided External divided External divided External divided by ...
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... APPLICATIONS Application Schematic IA3222B for worldwide telecom compliance Figure 23: Application schematic IA3222/IA3223 22 ...
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... R14 4.7k 1206 1 R15 20 1% 1206 2 U1, U2 IA3222B Option C16 2.2µF 6.3V 0603 (only if more signal headroom is needed at the low or lowest headroom setting) Option Q6 MMBTA06 (only if more signal headroom is needed at the low or lowest headroom setting) Option R18 4.7k 0603 (only if more signal headroom is needed at the low or lowest headroom setting) ...
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Application Schematic (Legacy TBR21 Current-Limit Support) TBR21 current limit is no longer in force in Europe but may still be required for certain countries, e.g. Algeria, Bahrain, Croatia, Estonia, Ghana, Ivory Coast, Lebanon, Morocco and Turkey. This application is suitable ...
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... R14 4.7k 1206 1 R15 20 1% 1206 2 U1, U2 IA3222B Option C16 1µF 16V 0603 (only if more signal headroom is needed at the low or lowest headroom setting) Option Q6 MMBTA06 (only if more signal headroom is needed at the low or lowest headroom setting) Option R18 4.7k 0603 (only if more signal headroom is needed at the low or lowest headroom setting) ...
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Component Discussion The application schematic (Figure 23) is intended as a high-density surface-mount solution. When using through-hole components, some changes may be possible in the design. Please contact IAI support for these issues. The main hook switch is composed of ...
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Sample Layout Layout Guidelines • Minimize trace lengths between U1, R1 and R15. • Disc capacitors and their connecting traces should be drawn exactly as shown, with 4.95mm (195 mils) diameters, 2.5mm (98.5 mils) spacing and 10-mil traces in between ...
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Interfacing the IA3223 The simplified block diagram below shows single ended interface to A/D and D/A. The analog interface consists of 3 pins: • TX – audio input • RX – audio output • ACREF – AC voltage reference There ...
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Interfacing Examples ( coupled) CODEC Tx ( coupled) Optional CODEC reference ( coupled) CODEC CODEC + - + - CODEC + - IA3223 3.0V reference Tx - ACRef + 100nF - ...
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LINE MONITORING Theory of Operation—On-Hook Line Status The IA3222/3223 chipset was designed to provide maximum information about the telephone line—both AC and DC—to allow intelligent line management, and to allow automatic telephone devices to share the line with human-controlled applications ...
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The most common spurious ring detection is due to pulse dialing. In Japan, 20 pulses per second used to be common. The simple way to prevent spurious ring detection from dial pulses is to set a sufficiently high ring-detection threshold. ...
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Line in Use and Line Disconnect The LIU detector line-voltage threshold detector. One of four levels (~2.5, 15, 22.5, and 30V) can be selected. Unfortunately, line-in-use status is ambiguous for voltages between 12V and 19V. Central Office ...
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Line Drop Line drop or wink is a complete drop in loop current from the Central Office switch, usually indicating call disconnect or call waiting depending on the duration of the drop. Drops over 500 ms indicate disconnect while shorter ...
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Measuring Loop-Current Changes through the Received Audio signal The Line Side senses line-current information and encodes it for the System Side offset superimposed onto the received audio data. Since modem DSP algorithms routinely remove low-frequency components from ...
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SURGES, ISOLATION AND EMC Among the three regulatory domains that DAAs must comply with (telecom, safety and EMC), safety and EMC tend to be highly intertwined. Designing for regulatory approval can sometimes compromise field reliability of DAAs. Historically, the dominant ...
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The net effect is that several kV of longitudinal transients can be put on the telephone line for any lightning strike on the power line that runs above the same telephone lines. Since ...
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Metallic (differential) surges arise from the longitudinal lightning surges causing either the asymmetric triggering of the primary arrestors, or arcing of only one side of the line to ground (if only one primary arrestor is functioning). To protect against metallic ...
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From the telephone system side, a line cross might occur if a power line falls across the telephone line shorting to one side of the line. Power-line cross is different than lightning surges because of its ...
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EMC Another key advantage of the IA3222/3223 chipset is that many applications do not require the usual telephone-line EMC suppression components. The 2 pF total value of the isolation capacitors presents significant impedance at VHF and UHF radiating frequencies. At ...
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RETURN LOSS AND TRANS-HYBRID RETURN LOSS Telephone devices transmit and receive bi-directionally down a twisted-pair line. All of the transmitted signal would be present on the receiver were it not for a cancellation circuit called hybrid or two-to-four-wire hybrid. A ...
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Trans-hybrid drift mostly arises from thermal effects due to heating of the Line Side both from the line current and the electronic environment. The IA3222 was designed to have very low thermal drift to ...
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PACKAGE INFORMATION QSOP-16 and QSOP-20 Packages MSOP-10 Package SOIC-8 Package (JEDEC Outline MS-012AA) IA3222/IA3223 42 ...
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... ORDERING INFORMATION IA3222/IA3223 DAA Chipset with Analog Interface DESCRIPTION IA3222A – Line Side US/Japan DAA IC IA3222B – Line Side Enhanced Worldwide DAA IC IA3223 – System Side Worldwide DAA IC IA3223A – System Side Worldwide DAA IC with pin hook control Silicon Labs, Inc. ...