SI3018-KS Silicon Laboratories Inc, SI3018-KS Datasheet
SI3018-KS
Specifications of SI3018-KS
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SI3018-KS Summary of contents
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... Si3056 MCLK 1 16 OFHK FSYNC 2 15 RGDT/FSD/M1 SCLK SDO 12 GND 5 SDI 6 11 AOUT/INT FC/RGDT 7 10 C1A RESET 8 9 C2A Si3018/19/ DCT2 IGND DCT 3 14 DCT3 C1B 12 QE2 5 C2B VREG 7 10 VREG2 8 9 RNG2 RNG1 US Patent # 5,870,046 US Patent # 6,061,009 Other Patents Pending ...
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... Si3018/19/10 2 Rev. 1.03 ...
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... Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.26. Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 5.27. Multiple Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 5.28. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.29. Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 5.30. In-Circuit Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.31. Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 5.32. Revision Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Appendix—UL1950 3rd Edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7. Pin Descriptions: Si3056 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 8. Pin Descriptions: Si3018/ Si3018/19/10 Rev. 1.03 Page 3 ...
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... Si3018/19/10 9. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10. Evaluation Board Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 11. Product Selection and Identification Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 12. Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 13. Package Outline: 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Silicon Laboratories Si3056 Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 4 Rev. 1.03 ...
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... The Si3056 specifications are guaranteed when the typical application circuit (including component tolerance) and the Si3056 and any Si3018 or Si3019 are used. See Figure 17 on page 18 for typical application schematic. 2. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. ...
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... Ring Detect Voltage* V Ring Frequency Ringer Equivalence Number REN *Note: The ring signal is guaranteed to not be detected below the minimum. The ring signal is guaranteed to be detected above the maximum. TIP Si3018 RING Figure 1. Test Circuit for Loop Characteristics 6 see Figure 1) Test Condition I ...
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... RGDT is not functional in this state Symbol Test Condition – pin PDN = 1, PDL = PDN = 1, PDL = 1 D Rev. 1.03 Si3018/19/10 Min Typ Max Unit 2.4 — — V — — 0.8 V 2.4 — — V — — 0.35 V –10 — 10 µA — 15 — mA — 9 — mA — ...
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... Si3018/19/10 Table 4. AC Characteristics (V = 3 °C for K-Grade; see Figure 17 on page 18 Parameter 1 Sample Rate 1 PLL Output Clock Frequency Transmit Frequency Response Receive Frequency Response Receive Frequency Response 2,3 Transmit Full Scale Level 2,4 Receive Full Scale Level 5,6,7 Dynamic Range ...
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... VIN = 1 kHz, –13 dBFS CID V CID ).+ 20 x log (RMS V /RMS noise). The RMS noise measurement excludes kHz, –3 dBFS 10300 Hz log(RMS V /RMS noise CID Rev. 1.03 Si3018/19/10 Min Typ Max — –78 — — –78 — — 50 — — 6 — — ...
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... Si3018/19/10 Table 5. Absolute Maximum Ratings Parameter DC Supply Voltage Input Current, Si3056 Digital Input Pins Digital Input Voltage Operating Temperature Range Storage Temperature Range Note: Permanent device damage can occur if the above absolute maximum ratings are exceeded. Restrict functional operation to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods might affect device reliability. Table 6. Switching Characteristics— ...
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... Figure 3. Serial Interface Timing Diagram (DCE = pF) L Symbol Min t 244 c t — dty t — — — sfc t 40 hfc t d1 D15 D14 D15 D14 Rev. 1.03 Si3018/19/10 Typ Max Unit 1/256 Fs — — % — — — — — ns — — ns — — ns — — – ...
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... Si3018/19/10 Table 8. Switching Characteristics—Serial Interface (Master Mode, DCE = 1, FSD = Charge Pump 3 1,2 Parameter Cycle Time, SCLK SCLK Duty Cycle Delay Time, SCLK ↑ to FSYNC ↑ Delay Time, SCLK ↑ to FSYNC ↓ Delay Time, SCLK ↑ to SDO valid Delay Time, SCLK ↑ to SDO Hi-Z Delay Time, SCLK ↑ ...
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... Figure 5. Serial Interface Timing Diagram (DCE = 1, FSD = pF) L Symbol Min t 244 c t — dty t — — — — — D15 D14 D13 D15 D14 Rev. 1.03 Si3018/19/10 Typ Max Unit 1/256 Fs — — % — — — — — — — ns — — – D15 ...
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... Si3018/19/10 Table 10. Switching Characteristics—Serial Interface (Slave Mode, DCE = 1, FSD = Charge Pump 3 Parameter Cycle Time, MCLK Setup Time, FSYNC ↑ before MCLK ↓ * Delay Time, FSYNC ↑ after MCLK ↓ * Setup Time, SDI before MCLK ↓ Hold Time, SDI After MCLK ↓ ...
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... F 0 (0.1 dB dB) –0.1 — –74 t — °C for K-Grade) A Symbol Min dB) –0.2 — –40 t — gd Rev. 1.03 Si3018/19/10 Typ Max Unit — 3.3 kHz — 3.6 kHz — 0.1 dB 4.4 — kHz — — dB 12/Fs — s Typ Max Unit — ...
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... Si3018/19/10 Figure 7. FIR Receive Filter Response Figure 8. FIR Receive Filter Passband Ripple For Figures 7–10, all filter plots apply to a sample rate kHz. 16 Figure 9. FIR Transmit Filter Response Figure 10. FIR Transmit Filter Passband Ripple Rev. 1.03 ...
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... Figure 11. IIR Receive Filter Response Figure 12. IIR Receive Filter Passband Ripple Figure 13. IIR Transmit Filter Response Si3018/19/10 Figure 14. IIR Transmit Filter Passband Ripple Figure 15. IIR Receive Group Delay Figure 16. IIR Transmit Group Delay Rev. 1.03 17 ...
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... Si3018/19/10 2. Typical Application Schematic 18 Rev. 1.03 ...
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... Value for C3 above is recommended for use with the Si3018. In voice appliations value of 3.9 nF X7R, 20%) is recommended to improve return loss performance 2. Several diode bridge configurations are acceptable, parts such as a single DF-04S or four 1N4004 diodes may be used (suppliers include General Semiconductor, Diodes Inc., etc.) 3 ...
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... Si3018/19/10 4. AOUT PWM Output Figure 18 illustrates an optional circuit to support the pulse width modulation (PWM) output capability of the Si3056 for call progress monitoring purposes. Set the PWME bit (Register 1, bit 3) to enable this mode AOUT Figure 18. AOUT PWM Circuit for Call Progress Table 13. Component Values— ...
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... Use the Si3010 line-side device for this configuration. The Si3010 contains all the features available on the Si3018, except the transmit and receive paths are optimized and tested only for modem connect rates up to 2400 bps. ...
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... Yes (HW interrupt) Yes (HW interrupt) Yes (HW interrupt Yes Yes Yes (MCLK active) Yes (MCLK active) Yes (MCLK active interrupts Yes Yes No Yes +3.2 dBm 0 dBm Rev. 1.03 Si3056 Si3018 Si3019 Yes Yes SSI SSI 3 kbps 56 kbps 16-bit 16-bit 8-bit 8-bit 16 kHz 16 kHz ...
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... Latvia 0 1 Lebanon 0 1 Note: 1. Supported for loop current ≥ 20 mA. 2. Available with Si3019 line-side only. 3. Available with Si3018 line-side only. 4. See "5.11.DC Termination" on page 27 for DCV and MINI settings. 5. ACIM is 0000 for data applications and 1010 for voice applications ILIM ...
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... USA 0 0 Yemen 0 0 Note: 1. Supported for loop current ≥ 20 mA. 2. Available with Si3019 line-side only. 3. Available with Si3018 line-side only. 4. See "5.11.DC Termination" on page 27 for DCV and MINI settings. 5. ACIM is 0000 for data applications and 1010 for voice applications ILIM ...
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... DCT pin voltage with the DVC[1:0] bits. 5.8. Line Voltage/Loop Current Sensing The Si3056 can measure loop current and line voltage with the Si3010, Si3018, and the Si3019 line-side devices. The 8-bit LCS2[7:0] and LCS[4:0] registers report loop current. The 8-bit LVS[7:0] register reports line voltage ...
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... Si3018/19/10 These registers can help determine the following: When on-hook, detect if a line is connected. When on-hook, detect if a parallel phone is off-hook. When off-hook, detect if a parallel phone goes on or off-hook. Detect if enough loop current is available to operate. When used in conjunction with the OPD bit, detect if an overcurrent condition exists. (See " ...
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... In the current limiting mode, the dc I/V curve is changed to a 2000 Ω slope above 40 mA, as shown in Figure 21. The DAA operates with 230 Ω feed, which is the maximum line feed specified in the TBR21 standard. Rev. 1.03 Si3018/19/10 FCC DCT Mode Loop Current (A) 27 ...
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... The Si3056 has four ac termination impedances with the Si3018 line-side device and sixteen ac termination impedances with the Si3019 line-side device. The ACT and ACT2 bits select the ac impedance on the Si3018 line-side device. The ACIM[3:0] bits select the ac impedance on the Si3019. The available ac termination settings are listed for the line-side devices in Tables 17 and 18 ...
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... The first method to monitor ring detection output uses the RGDT pin. When the RGDT pin is used, it defaults Si3018/19/10 to active low, but can be changed to active high by setting the RPOL bit (Register 14, bit 1). This pin is a standard CMOS output. If multiple RGDT pins are connected to a single input, the combined pullup or pulldown resistance should equal 4.7 k Ω ...
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... Si3018/19/10 When RFWE is 1, DTX sits at approximately +1228 while the RNG1-RNG2 voltage is between the thresholds. When the ring becomes positive, DTX transitions to +32767. When the ring signal goes near 0, DTX remains near 1228. As the ring becomes negative, the DTX transitions to –32768. This repeats in cadence with the ring signal ...
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... Because these components are expensive and few countries utilize billing tones, this filter is typically on placed in an external dongle or added as a population PK option for these countries. Figure 22 shows an example billing tone filter. Rev. 1.03 Si3018/19/10 31 ...
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... Si3018/19/ TIP From Line C3 RING Figure 22. Billing Tone Filter L1 must carry the entire loop current. The series resistance of the inductors is important to achieve a narrow and deep notch. This design has more than attenuation at both 12 kHz and 16 kHz. Table 19. Component Values—Optional Billing ...
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... Type II CID. Do not continue CID data reception. Si3018/19/10 f. Set the OH bit to 1 (or drive the OFHK pin to the active state) to return to an off-hook state. After returning to an off-hook state and waiting 8 ms for the off-hook counter, normal data transmission and reception can proceed ...
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... Si3018/19/10 O ff-Hook Counter LIN E and C alibration O n-H ook (402. nom inally [ [ Notes: 1. The off-hook counter and calibrations prevent transmission or reception of data for 402.75 ms (default) for the line voltage to settle. 2. The caller alert signal (CAS) tone transmits from the CO to signal an incoming call. ...
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... ILIM bit (Register 26). When ILIM = 0, the overload detection threshold equals 160 mA. When ILIM = 1, the overload detection threshold equals 60 mA. The OPE bit should always be cleared before going off-hook. To Link Si3056 Figure 24. Si3018/19/10 Signal Flow Diagram TGA2 SDI TXG2 IIRE RGA3 SDO ...
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... Si3018/19/10 5.24. Filter Selection The Si3056 supports additional filter selections for the receive and transmit signals as defined in Table 11 and Table 12 on page 15. The IIRE bit (Register 16, bit 4) selects between the IIR and FIR filters. The IIR filter provides a shorter, but non-linear, group delay alternative to the default FIR filter and only operates with an 8 kHz sample rate ...
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... Two methods exist for requesting a secondary frame to transfer control information. The default powerup mode uses the LSB of the 16-bit transmit (TX) data word as a flag to request a secondary transfer. Only 15-bit TX data is transferred, which results in a small loss of SNR but Rev. 1.03 Si3018/19/10 F MCLK ≥ 144 kHz F ...
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... Si3018/19/10 provides software control of the secondary frames alternative method, the FC pin can serve as a hardware flag for requesting a secondary frame. The external DSP can turn on the 16-bit TX mode by setting the SB bit (Register 1, bit 0). In the 16-bit TX mode, the hardware FC pin must be used to request secondary transfers ...
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... For the start-up loopback test mode, line-side power is not necessary and no off-hook sequence is required. The start-up test mode is enabled by default. When the PDL bit (Register 6, bit 4) is set (the default case), the line-side powerdown mode and the DSP-side digital loop-back mode. Data received on SDI Rev. 1.03 Si3018/19/10 39 ...
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... Si3018/19/10 passes through the internal filters and transmitted on SDO which introduces approximately attenuation on the SDI signal received. The group delay of both transmit and receive filters exists between SDI and SDO. Clearing the PDL bit disables this mode and the SDO data is switched to the receive data from the line-side ...
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... Secondary Prim ary D15 – (Software FC Bit) Secondary XMT Data Data Secondary RCV Data Data 256 SCLKS Rev. 1.03 Si3018/19/10 Si3010 0001 0010 0011 0100 0101 0110 (CF2) 41 ...
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... Si3018/19/10 Com m unications Fram e 1 (CF1) FSYNC Prim ary FC 0 D15–D0 SDI XMT Data SDO RCV Data 16 SCLKS 128 SCLKS Figure 28. Hardware FC/RGDT Secondary Request FSYNC (mode 0) FSYNC (mode 1) SDI SDO Figure 29. Secondary Communication Data Format—Read Cycle 42 Secondary Prim ary ...
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... Slave1 Comments Primary frames with secondary frame requested via SDI[ Figure 31. Daisy Chaining of a Single Slave (Pulse FSD) D15 D14 D13 D12 D11 D10 SCLKs Master Master Master Master Rev. 1.03 Si3018/19/ Secondary Frame (Control) 128 SCLKs Slave1 Slave1 Slave1 Slave1 43 ...
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... Si3018/19/10 Master Serial Mode 1 Reg 14: NSLV = 1, SSEL = 2, FSD = 1, DCE = 1 Slave 1 Serial Mode 2 Reg 14 Reset values: NSLV = 1, SSEL = 3, FSD = 1, DCE = 1 Prim ary Frame (Data) Master FSYNC Master FSD/ 16 SCLKs 16 SCLKs Slave1 FSYNC SDI [0] 1 SDI [15..1] Master SDO [0] 1 SDO[15..1] Master Comments Primary frames with secondary frame requested via SDI[ Figure 32 ...
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... Si3018/19/10 Rev. 1.03 45 ...
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... Si3018/19/10 M aster Serial M ode 0 Reg 14: NSLV = 1, SSEL = 2, FSD = 0, DCE = 1 Slave 1 Serial M ode 2 Reg 14 Reset values: NSLV = 1, SSEL = 3, FSD = 1, DCE = 1 Primary Frame (Data) 16 SCLKs M aster FSYNC M aster FSD/ Slave1 FSYNC SDI [0] 1 SDI [15..1] M aster SD0 [0] 1 SD0 [15..1] M aster Com m ents Prim ary fram es with secondary fram e requested via SDI[ Figure 34 ...
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... Host SCLK SDO SDI FSYNC INTO 47 kΩ 47 kΩ VCC 47 kΩ Figure 36. Typical Connection for Multiple DAAS Rev. 1.03 Si3018/19/10 MCLK Si3056—Master MCLK SCLK SDI SDO FSYNC FC/RGDT RGDT/FSD/M1 VCC M0 47 kΩ Si3056—Slave 1 MCLK NC SCLK FSYNC SDI ...
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... Line Current/Voltage Threshold Interrupt Control 45–52 Programmable Hybrid Register 1–8 53–58 Reserved 59 Spark Quenching Control Notes: 1. Bit is available for Si3019 line-side device only. 2. Bit is available for Si3010 and Si3018 line-side device only. 48 Table 23. Register Summary Bit 7 Bit 6 Bit 5 Bit 4 SR PWMM[1:0] INTE ...
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... Operation is in 15-bit mode, and the LSB of the data field indicates that a secondary frame is required The serial port is operating in 16-bit mode and requires a secondary frame sync signal, FC, to initiate control data reads/writes PWME IDL R/W R/W R/W Function Rev. 1.03 Si3018/19/ R/W 49 ...
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... Si3018/19/10 Register 2. Control 2 Bit Name INTE INTP Type R/W R/W Reset settings = 0000_0011 Bit Name 7 INTE Interrupt Pin Enable The AOUT/INT pin functions as an analog output for call progress monitoring purposes The AOUT/INT pin functions as a hardware interrupt pin. 6 INTP Interrupt Polarity Select. ...
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... TIP and RING was switched polarity change on TIP and RING does not cause an interrupt on the AOUT/INT pin polarity change on TIP and RING causes an interrupt on the AOUT/INT pin BTDM DODM LCSOM DLCSM R/W R/W R/W R/W Function Rev. 1.03 Si3018/19/10 D0 POLM R/W 51 ...
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... Si3018/19/10 Register 4. Interrupt Source Bit Name RDTI ROVI FDTI Type R/W R/W R/W Reset settings = 0000_0000 Bit Name 7 RDTI Ring Detect Interrupt ring signal is not occurring ring signal is detected. If the RDTM (Register 3) and INTE (Register 2) bits are set a hard- ware interrupt occurs on the AOUT/INT pin. This bit must be written cleared. The RDI bit (Register 2) determines if this bit is set only at the beginning of a ring pulse the end of a ring pulse as well ...
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... Enables operation of the off-hook pin Off-Hook Line-side device on-hook Causes the line-side device to go off-hook. This bit operates independently of the OHE bit and is a logic OR with the off-hook pin when enabled. Function OPOL ONHM RDT OHE R/W R/W R R/W Function Rev. 1.03 Si3018/19/ R/W 53 ...
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... Si3018/19/10 Register 6. DAA Control 2 Bit Name Type Reset settings = 0001_0000 Bit Name 7:5 Reserved Read returns zero. 4 PDL Powerdown Line-Side Device Normal operation. Program the clock generator before clearing this bit Places the line-side device in lower power mode. 3 PDN Powerdown System-Side Device. ...
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... Reserved Read returns zero. 0 DDL Digital Data Loopback Normal operation Audio data received on SDI and loops it back out to SDO before the TX and RX filters. Outputted data is identical to inputted data N[7:0] R/W Function M[7:0] R/W Function Function Rev. 1.03 Si3018/19/ DDL R/W 55 ...
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... Bit Name 7:4 LSID[3:0] Line-Side ID Bits. These four bits will always read one of the following values depending on which line-side device is used. Si3018 Si3019 Si3010 3:0 REVA[3:0] System-Side Revision. Four-bit value indicating the revision of the system-side device. Register 12. Line-Side Device Status Bit ...
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... Register 13. Line-Side Device Revision Bit Name 0 Type Reset settings = xxxx_xxxx Bit Name 7 Reserved Read returns zero This bit always reads a zero. 5:2 REVB[3:0] Line-Side Device Revision. Four-bit value indicating the revision of the line-side device. 1:0 Reserved Read returns zero REVB[3:0] R Function Rev. 1.03 Si3018/19/ ...
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... Si3018/19/10 Register 14. Serial Interface Control Bit Name NSLV[2:0] Type R/W Reset settings = 0000_0000 (serial mode 0,1) Reset settings = 0011_1101 (serial mode 2) Bit Name 7:5 NSLV[2:0] Number of Slaves devices. 000 = 0 slaves. Redefines the FC/RGDT and RGDT/FSD pins. 001 = 1 slave device 010 = 2 slave devices 011 = 3 slave devices 100 = 4 slave devices (For four or more slave devices, the FSD bit MUST be set ...
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... Note: Write these bits to zero when using the finer resolution transmit and receive gain/attenuation registers 38–41 available only with the Si3019 line-side device RXM ARX[2:0] R/W R/W Function Rev. 1.03 Si3018/19/ ...
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... ACT2 OHS ACT Type RW R/W R/W Reset settings = 0000_0000 Bit Name 7 ACT2 AC Termination Select 2 (Si3018 line-side device only). Works with the ACT bit to select one of four ac terminations: ACT2 ACT The global complex impedance meets minimum return loss requirements in countries that require a complex ac termination ...
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... Normal receive input level Excessive receive input level. 0 BTD Billing Tone Detected. This bit is set if a billing tone is detected. Writing a zero to BTE clears this bit billing tone detected Billing tone detected OPE BTE ROV R/W R/W R/W Function Rev. 1.03 Si3018/19/10 D0 BTD R 61 ...
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... Si3018/19/10 Register 18. International Control 3 Bit Name Type Reset settings = 0000_0000 Bit Name 7:2 Reserved Read returns zero or one. 1 RFWE Ring Detector Full-Wave Rectifier Enable. When RNGV (Register 24) is disabled, this bit controls the ring detector mode and the asser- tion of the RGDT pin. When RNGV is enabled, this bit configures the RGDT pin to either follow ...
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... ILIM bit (Register 26). OPD ILIM OVL DOD R R Function Overcurrent Threshold Overcurrent Status 160 mA No overcurrent condition exists overcurrent condition exists 160 mA An overcurrent condition has been detected overcurrent condition has been detected Rev. 1.03 Si3018/19/10 D0 OPD R 63 ...
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... Si3018/19/10 Register 20. Call Progress Receive Attenuation Bit Name Type Reset settings = 0000_0000 Bit Name 7:0 ARM[7:0] AOUT Receive Path Attenuation. When decremented from the default setting, these bits linearly attenuate the AOUT receive path signal used for call progress monitoring. Setting the bits to all 0s mutes the AOUT receive path ...
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... To compensate for error margin and ensure a sufficient ring detection window recom- mended that the calculated value of RMX[5:0] be incremented RMX[5:0] R/W Function RDLY[1:0] Delay 256 512 1792 RAS 5:0 ≥ -------------------------------------------- - RMX RAS RMX 5:0 – × 2 f_max Rev. 1.03 Si3018/19/ ≤ × ...
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... Si3018/19/10 Register 23. Ring Validation Control 2 Bit Name RDLY[2] RTO[3:0] Type R/W Reset settings = 0010_1101 Bit Name 7 RDLY[2] Ring Delay Bit 2. This bit, in combination with the RDLY[1:0] bits (Register 22), set the amount of time between when a ring signal is validated and when a valid ring signal is indicated. ...
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... To compensate for error margin and ensure a sufficient ring detection window recom- mended that the calculated value of RMX[5:0] be incremented RAS[5:0] R/W Function RAS 5:0 ≥ ------------------------------------------ - RMX RAS RMX 5:0 – × × 2 f_min 2 ms Rev. 1.03 Si3018/19/ ≤ 67 ...
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... Si3018/19/10 Register 25. Resistor Calibration Bit Name RCALS RCALM RCALD Type R R/W R/W Reset settings = xx0x_xxxx Bit Name 7 RCALS Resistor Auto Calibration Resistor calibration is not in progress Resistor calibration is in progress. 6 RCALM Manual Resistor Calibration calibration Initiate manual resistor calibration. (After a manual calibration has been initiated, this bit must be cleared within 1 ms ...
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... Current limiting mode enabled. Limits loop current to a maximum per the TBR21 standard. 0 DCR DC Impedance Selection Ω dc termination is selected. Use this mode for all standard applications 800 Ω dc termination is selected ILIM R/W R/W Function 3.1 V 3.2 V 3. Rev. 1.03 Si3018/19/10 D0 DCR R/W 69 ...
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... Si3018/19/10 Register 27. Reserved Bit Name Type Reset settings = xxxx_xxxx Bit Name 7:0 Reserved Do not read or write. Register 28. Loop Current Status Bit Name Type Reset settings = 0000_0000 Bit Name 7:0 LCS2[7:0] Loop Current Status. Eight-bit value returning the loop current. Each bit represents 1 loop current. ...
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... Revision C or earlier) 1010 = 200 Ω + (680 Ω || 100 nF) (China) (line-side Revision E or later) 1011 = 600 Ω + 2.16 µF 1100 = 900 Ω µF 1101 = 900 Ω + 2.16 µF 1110 = 600 Ω µF 1111 = Global impedance FULL2 ACIM[3:0] R/W R/W Function Rev. 1.03 Si3018/19/ ...
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... Si3018/19/10 Register 31. DAA Control 3 Bit Name FULL FOH[1:0] Type R/W R/W Reset settings = 0010_0000 Bit Name 7 FULL Full Scale Transmit and Receive Mode (Si3019 line-side device only Default Transmit/receive full scale. This bit changes the full scale of the ADC and DAC from 0 min to +3.2 dBm into a 600 Ω load (or 1 dBV into all reference impedances) ...
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... TXG2[3:0] Result 0000 0 dB gain or attenuation is applied to the transmit path. 0001 1 dB gain is applied to the transmit path. : 11xx 12 dB gain is applied to the transmit path. 0001 1 dB attenuation is applied to the transmit path. : 1111 15 dB attenuation is applied to the transmit path. Rev. 1.03 Si3018/19/ ...
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... Si3018/19/10 Register 39. RX Gain Control 2 (Si3019 Line-Side Device Only) Bit Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 RGA2 Receive Gain or Attenuation Incrementing the RXG2[3:0] bits results in gaining up the receive path Incrementing the RXG2[3:0] bits results in attenuating the receive path. ...
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... TXG3[3:0] Result 0000 0 dB gain or attenuation is applied to the transmit path. 0001 0.1 dB gain is applied to the transmit path. : 1111 1.5 dB gain is applied to the transmit path. 0001 0.1 dB attenuation is applied to the transmit path. : 1111 1.5 dB attenuation is applied to the transmit path. Rev. 1.03 Si3018/19/ ...
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... Si3018/19/10 Register 41. RX Gain Control 3 (Si3019 Line-Side Device Only) Bit Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 RGA3 Receive Gain or Attenuation Incrementing the RXG3[3:0] bits results in gaining up the receive path Incrementing the RXG3[3:0] bits results in attenuating the receive path. ...
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... LCS2 or LVS register falling below the value in the CVT[7:0] register The current / voltage threshold is triggered by the absolute value of the number in the either the LCS2 or LVS register rising above the value in the CVT[7:0] Register CVT[7:0] R/W Function CVI CVS CVM R/W R/W R/W Function Rev. 1.03 Si3018/19/ CVP R/W 77 ...
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... Si3018/19/10 Register 45. Programmable Hybrid Register 1 Bit Name Type Reset settings = 0000_0000 Bit Name 7:0 HYB1[7:0] Programmable Hybrid Register 1. These bits are programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. This register represents the first tap in the 8-tap filter. When this register is set to all 0s, this filter stage does not effect on the hybrid response. See " ...
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... This register represents the fourth tap in the 8-tap filter. When this register is set to all 0s, this filter stage does not effect on the hybrid response. See "5.13.Transhybrid Balance" on page 29 for more information on selecting coefficients for the programmable hybrid HYB3[7:0] R/W Function HYB4[7:0] R/W Function Rev. 1.03 Si3018/19/ ...
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... Si3018/19/10 Register 49. Programmable Hybrid Register 5 Bit Name Type Reset settings = 0000_0000 Bit Name 7:0 HYB5[7:0] Programmable Hybrid Register 5. These bits are programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. This register represents the fifth tap in the 8-tap filter. When this register is set to all 0s, this filter stage does not effect on the hybrid response. See " ...
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... See "5.13.Transhybrid Balance" on page 29 for more information on selecting coefficients for the programmable hybrid. Register 53-58 Reserved Bit Name Type Reset settings = xxxx_xxxx Bit Name 7:0 Reserved Do not write to these register bits HYB7[7:0] R/W Function HYB8[7:0] R/W Function Function Rev. 1.03 Si3018/19/ ...
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... Si3018/19/10 Register 59. Spark Quenching Control Bit Name SQ1 Type R/W Reset settings = xxxx_xxxx Bit Name 7 Reserved Always write this bit to zero. Spark Quenching. 6 SQ1 This bit, in combination with the OHS bit (Register 16), and the OHS2 bit (Register 31), sets the amount of time for the line-side device to go on-hook. The on-hook speeds specified are measured from the time the OH bit is cleared until loop current equals zero ...
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... Consult with a professional testing agency during the design of the product to determine which tests apply to the system. 75 Ω @ 100 MHz 1.25 A 1.25 A RV1 Rev. 1.03 Si3018/19/10 C8 FB1 TIP 75 Ω @ 100 MHz FB2 RING C9 C8 ...
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... Si3018/19/10 7. Pin Descriptions: Si3056 Pin # Pin Name 1 MCLK Master Clock Input. High speed master clock input. Generally supplied by the system crystal clock or modem/DSP. 2 FSYNC Frame Sync Output. Data framing signal that indicates the start and stop of a communication/data frame. 3 SCLK Serial Port Bit Clock Output. ...
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... It is also the second of two mode select pins that selects the operation of the serial port/DSP interface when RESET is deasserted. 16 OFHK Off-Hook. An active low input control signal that provides a termination across TIP and RING for line seizing and pulse dialing, Si3018/19/10 Description Rev. 1.03 85 ...
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... Si3018/19/10 8. Pin Descriptions: Si3018/19/10 Table 25. Si3018/19/10 Pin Descriptions Pin # Pin Name 1 QE Transistor Emitter. Connects to the emitter of Q3. 2 DCT DC Termination. Provides dc termination to the telephone network Receive Input. Serves as the receive side input from the telephone network Isolation Capacitor 1B. Connects to one side of isolation capacitor C1. Used to communicate with the system- side device ...
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... Table 25. Si3018/19/10 Pin Descriptions (Continued) Pin # Pin Name 13 QB Transistor Base. Connects to the base of transistor Q4. 14 DCT3 DC Termination 3. Provides dc termination to the telephone network. 15 IGND Isolated Ground. Connects to ground on the line-side interface. 16 DCT2 DC Termination 2. Provides dc termination to the telephone network. Si3018/19/10 Description Rev. 1.03 ...
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... The ordering part number for Silicon Labs devices may include the revision letter (example Si3056-D-KS, where D is the die revision letter). Refer to "12.Product Identification" on page 90 for more information on part naming conventions. 88 Digital Line (SOIC) (SOIC) Si3019-KS GCI Si3018-KS GCI Si3056-KS Si3018-KS Si3056-KS Si3019-KS Si3056-KS Si3010-KS Si3019-X-FS GCI Si3018-X-FS GCI Si3018-X-FS Si3056-FS Si3019-X-FS ...
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... Si3010 Daughtercard Only Platform Intended Use Direct Connection use with included Windows based SW program. or DSP (in customer application or to another EVB). Direct Connection to processor or DSP (in customer applica- tion). Rev. 1.03 Si3018/19/10 Includes Includes Platform DAA Board? Daughter Card? ® - Yes Yes (PPT) ...
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... Si3018/19/10 11. Product Selection and Identification Guide Device Finished Goods Part Number Si3056 Si3056-X-KS Commercial part Si3056 Si3056-X-FS Commercial part, lead-free version Si3056 Si3056-X-XS4 Customer-specific bond option Si3056 Si3056-X-ZS4 Customer-specific bond option, lead-free version Si3056 Si3056-X-XS5 Customer-specific bond option Si3056 Si3056-X-ZS5 Customer-specific bond option, lead-free version ...
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... A1 γ Millimeters Symbol Min Max A 1.35 1.75 A1 .10 .25 B .33 .51 C .19 .25 D 9.80 10.00 E 3.80 4.00 e 1.27 BSC H 5.80 6.20 h .25 .50 L .40 1.27 γ 0.10 θ 0º aaa 0.25 bbb 0.25 Rev. 1.03 Si3018/19/ Detail F C See Detail F 8º 91 ...
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... Si3018/19/ OCUMENT HANGE IST Revision 0.2 to Revision 0.71 Updated list of applications on cover page, including ability to support V.92 modems. Updated Transmit Full Scale Level test condition and note in Table 4 (AC Characteristics) for description of VCID and DRCID. Updated specifications in Table 7, Table 8, and Table 9 (Switching Characteristics) and Figure 3, Figure 4, and Figure 5. Updated “ ...
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... Line-Side Only)" on page 25 of Functional description to include new enhanced full scale mode. The following bits have been added, but will only be supported with Si3018/19/10 Revision E or later line- side devices. Added FULL2 bit on p. 73. Added RG1 and GCE bits on p. 89. ...
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... Si3018/19/ ILICON ABORATORIES Application Note 13: Silicon DAA Software Guidelines Application Note 16: Multiple Device Support Application Note 17: Designing for International Safety Compliance Application Note 67: Layout Guidelines Application Note 72: Ring Detection/Validation with the Si305x DAAs Application Note 84: Digital Hybrid with the Si305x DAAs ...
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... N : OTES Si3018/19/10 Rev. 1.03 95 ...
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... Si3018/19/ ONTACT NFORMATION Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: SiDAAinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...