SI3220-GQ Silicon Laboratories Inc, SI3220-GQ Datasheet - Page 74

• Manufacturer Part Number: SI3220-GQ
• Description: IC SLIC/CODEC DUAL-CH 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: ProSLIC®r

Specifications of SI3220-GQ

• Function: Subscriber Line Interface Concept (SLIC), CODEC
• Interface: GCI, PCM, SPI
• Number Of Circuits: 2
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 65mA
• Power (watts): 941mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: *
• Includes: Battery Switching, BORSCHT Functions, DTMF Generation and Decoding, FSK Tone Generation, Modem and Fax Tone Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si3220/Si3225
PCM Interface
The
programmable interface for the transmission and
reception of digital PCM samples. PCM data transfer is
controlled by the PCLK and FSYNC inputs, PCM Mode
Select,
PCMTXLO), and PCM Receive Start Count (PCMRXHI/
PCMRXLO) registers. The interface can be configured
to support from 4 to 128 8-bit timeslots in each frame.
This corresponds to PCLK frequencies of 256 kHz to
8.192 MHz
1.536 MHz, and 1.544 MHz are also available for T1
and E1 support.) Timeslots for data transmission and
reception are independently configured with the
PCMTXHI, PCMTXLO, PCMRXHI, and PCMRXLO.
Setting the correct starting point of the data configures
the part to support long FSYNC and short FSYNC
variants, IDL2 8-bit, 10-bit, and B1 and B2 channel time
slots. DTX data is high-impedance except for the
74
CS
SCLK
SDI
SDO
Dual
PCM
ProSLIC
in
PCLK_CNT
Transmit
power-of-2
FSYNC
PCLK
DRX
DTX
Figure 51. Example, Timeslot 1, Short FSYNC (TXS/RXS
CONTROL
devices
HI-Z
Figure 50. RAM Read Operation via a 16-Bit SPI Port
Start
0
increments.
1
contain
Count
MSB
MSB
2
3
ADDRESS
(PCMTXHI/
a
4
(768 kHz,
flexible
5
6
Rev. 1.0
7
duration of the 8-bit PCM transmit. DTX returns to high-
impedance on the negative edge of PCLK during the
LSB or on the positive edge of PCLK following the LSB.
This is based on the setting of the PCMTRI bit of the
PCM Mode Select register. Tristating on the negative
edge allows the transmission of data by multiple
sources in adjacent timeslots without the risk of driver
contention. In addition to 8-bit data modes, a 16-bit
mode is provided for testing. This mode can be
activated via the PCMF bits of the PCM Mode Select
register.
PCMRXHI/PCMRXLO register greater than the number
of PCLK cycles in a sample period stops data
transmission because neither PCMTXHI/PCMTXLO nor
PCMRXHI/PCMRXLO equal the PCLK count. Figures
51–54 illustrate the usage of the PCM highway interface
to adapt to common PCM standards.
8
LSB
LSB
9
10
Data [15:8]
Setting
11
12
HI-Z
13
the
14
15
PCMTXHI/PCMTXLO
=
16
Data [7:0]
1)
17
18
or