MAX2991ECM+ Maxim Integrated Products, MAX2991ECM+ Datasheet - Page 18

IC TXRX FRONT-END 48LQFP

MAX2991ECM+

Manufacturer Part Number
MAX2991ECM+
Description
IC TXRX FRONT-END 48LQFP
Manufacturer
Maxim Integrated Products
Type
General Purposer
Datasheet

Specifications of MAX2991ECM+

Function
Analog Front-End Transceiver
Interface
SPI Serial
Number Of Circuits
1
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
36mA, 70mA
Power (watts)
1.54W
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LQFP
Includes
Automatic Gain Control (AGC)
Product
Analog Front End
Data Rate
1.2 Msps
Interface Type
Digital
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Supply Current
36 mA, 70 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Maximum Power Dissipation
1535 mW
Mounting Style
SMD/SMT
Number Of Channels
2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 8. Interfacing with the MAX2990
The MAX2991 uses a reference clock to tune Rx and Tx
filters. In default mode, Rx clock is used as the reference
source for the process tuner. Process tuner clock can
be set to any one of RXCLK, TXCLK, or REFCLK clock
sources. PTUN1<4:3> sets the clock source.
For clock rates other than 19.2MHz, update the DPTUN1
and DPTUN2 registers accordingly.
Power-Line Communications (PLC) Integrated
Analog Front-End Transceiver
Table 2. Process Tuner Configuration, PTUN1<5:0>, Address: 0x03, Default: 0x13
Table 3. Summary of Calculations Needed when Process Tuner Clock Rate is Changed
18
_____________________________________________________________________________________
Programming the MAX2991 for Different
CLOCK RATE
PTCLKMUX
BIT NAME
(MHz)
19.2
9.6
Applications Information
Programming the Process
LOCATION
(52.7 x FREQUENCY)
Tuner Reference Clock
COUNTER LIMIT
4, 3
1011.84
505.92
Sampling Rates
MAX2991
AFE
DEFAULT
RXCONV
TXCONV
RXDATA
TXDATA
AGCCS
10
RXCLK
TXCLK
ENRX
ENTX
RST
DPTUN1
0x3F4
0x1F9
Process tuner clock selection:
00 or 01: REFCLK
10: RXCLK
11: TXCLK
Table 3 summarizes the calculation for the default clock
rate and another one.
The ADC sampling rate is the clock rate divided by 16.
The sampling rate is adjustable from 200ksps to 1.2ksps
in 200ksps steps.
The interface to the MAX2991 AFE device uses a bidirec-
tional bus to transfer the digital data from the ADC and
to the DAC. Handshaking lines help accomplish the data
transfer as well as operation of the AFE. Figure 8 shows
the interface between the MAX2991 and the MAX2990.
P3.7
P3.8
P2.2
P3.6
P3.0
P3.5
P3.2
P3.3
P3.4
P3.1
Interfacing to the MAX2990 Baseband
(0.3125 x FREQUENCY)
HYSTERESIS RANGE
BASEBAND
MAX2990
6.0
3.0
FUNCTION
DPTUN2
0x006
0x003

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