M-8870-01SM Clare, M-8870-01SM Datasheet - Page 6

• Manufacturer Part Number: M-8870-01SM
• Description: IC RECEIVER DTMF CMOS LP 18-SOIC
• Manufacturer: Clare

Specifications of M-8870-01SM

• Function: DTMF Receiver
• Number Of Circuits: 1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 3mA
• Power (watts): 35mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: *
• Includes: Decoder, Dial Tone Suppression
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Interface: -

M-8870
6
AC Characteristics
All voltages referenced to V
*Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Notes:
1. dBm = decibels above or below a reference power of 1 mW into a 600Ω load.
2. Digit sequence consists of all 16 DTMF tones.
3. Tone duration = 40 ms. Tone pause = 40 ms.
4. Nominal DTMF frequencies are used, measured at GS.
5. Both tones in the composite signal have an equal amplitude.
6. Bandwidth limited (0 to 3 kHz) Gaussian noise.
7. The precise dial tone frequencies are (350 and 440 Hz) ± 2%.
8. For an error rate of better than 1 in 10,000.
9. Referenced to lowest level frequency component in DTMF signal.
10. Minimum signal acceptance level is measured with specified maximum frequency deviation.
11. Input pins defined as IN+, IN-, and OE.
12. External voltage source used to bias V
13. This parameter also applies to a third tone injected onto the power supply.
14. Referenced to Single - Ended Input Configuration on page 3. Input DTMF tone level at -28 dBm.
Valid input signal levels (each tone
of composite signal)
Positive twist accept
Negative twist accept
Frequency deviation accept limit
Frequency deviation reject limit
Third tone tolerance
Noise tolerance
Dial tone tolerance
Tone present detection time
Tone absent detection time
Minimum tone duration accept
Maximum tone duration reject
Minimum interdigit pause accept
Maximum interdigit pause reject
Propagation delay (St to Q)
Propagation delay (St to StD)
Output data setup (Q to StD)
Propagation delay (OE to Q), enable
Propagation delay (OE to Q), disable
Crystal clock frequency
Clock output (OSC2), capacitive load
Parameter
SS
unless otherwise noted. For typical values V
REF
.
Symbol
t
t
t
t
t
t
f
C
QStD
t
t
t
t
PStD
REC
REC
t
PTD
PTE
CLK
DO
DP
DA
PQ
-
-
-
-
-
-
-
-
-
ID
LO
DD
3.5759
±3.5%
Min
27.5
= 5.0 V, V
+18
-29
-25
0.5
20
20
5
-
-
-
-
-
-
-
-
-
-
-
-
www.clare.com
SS
= 0 V, TA = 25°C, f
3.5795
Typ*
+22
300
-16
-12
4.0
50
8
3
6
9
-
-
-
-
-
-
-
-
-
-
-
± 1.5% + 2 Hz
3.5831
CLK
Max
869
8.5
+1
10
10
14
40
40
11
16
60
30
-
-
-
-
-
-
-
-
= 3.579545 MHz.
mVRMS
Units
Nom.
Nom.
dBm
MHz
ms
ms
ms
ms
ms
ms
dB
dB
dB
dB
dB
µs
µs
µs
ns
ns
pF
User adjustable (see Basic Steering
Circuit and Guard Time Adjustment
See Timing Diagram on page 7
R
L
on pages 3 and 4.)
2,3,4,5,8,9,13,14
= 10 kΩ, C
2,3,4,5,6,8,9
2,3,4,5,7,8,9
1,2,3,4,5,8
2,3,5,8,10
OE = VDD
Notes
2,3,4,8
2,3,5
-
-
L
= 50 pF
Rev. 3