SI3210-KT Silicon Laboratories Inc, SI3210-KT Datasheet - Page 138

• Manufacturer Part Number: SI3210-KT
• Description: IC PROSLIC W/DC-DC CONV 38TSSOP
• Manufacturer: Silicon Laboratories Inc
• Series: ProSLIC®r
• Type: ProSLIC Programmable CMOS SLICr

Specifications of SI3210-KT

• Package / Case: *
• Function: Subscriber Line Interface Concept (SLIC), CODEC
• Interface: PCM, SPI
• Number Of Circuits: 1
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 88mA
• Power (watts): 700mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Includes: BORSCHT Functions, DTMF Generation and Decoding, FSK Generation, Pulse Metering Generation, Voice Loopback Test Modes
• Product: Telecom
• Supply Voltage (min): 3.13 V
• Supply Current: 4 mA
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Si3210/Si3211
8.3.2. PCB Land Pattern: 16-Pin ESOIC
Figure 38 illustrates the recommended land pattern for the Si3201 SOIC-16 package. Table 53 lists the values for
the dimensions shown in the illustration.
138
Y2
Notes:
General
Solder Mask Design
Stencil Design
Card Assembly
Dimension
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ASME Y14.5M-1994.
3. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X175-17N.
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
2. The stencil thickness should be 0.125mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for
C1
X1
Y1
X2
mask and the metal pad is to be 60m minimum, all the way around the pad.
to assure good solder paste release.
Small Body Components.
E
Table 53. SOIC-16 PCB Land Pattern Dimensions
Figure 38. SOIC-16 PCB Land Pattern Drawing
Pin pad column spacing
Thermal pad length
Thermal pad width
Pin pad row pitch
Pin pad length
Pin pad width
Feature
Rev. 1.5
5.30
0.50
1.45
2.20
3.50
Min
1.27 BSC
Max
5.40
2.30
3.60
0.60
1.55