MAX3107EAG+ Maxim Integrated Products, MAX3107EAG+ Datasheet - Page 29

• Manufacturer Part Number: MAX3107EAG+
• Description: IC UART SPI/I2C 128 FIFO 24SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX3107EAG+

• Features: Internal Oscillators
• Number Of Channels: 4, QUART
• Fifo's: 128 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.35 V ~ 3.6 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Data Rate: 24 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.71 V
• Supply Current: 4 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SpclCharInt—Special Character Interrupt Register
Bits 7 and 6: No Function
Bit 5: MultiDropInt
The MultiDropInt interrupt is set when the MAX3107 receives an address character in 9-bit multidrop mode
(MODE2[6] is 1). This bit is cleared when SpclCharInt is read. The SpclCharInt bit can be routed to ISR[1] by enabling
SpclChrIntEn[5].
Bit 4: BREAKInt
The BreakInt interrupt is set when a line BREAK (RX low for longer than one character length) is detected by the
receiver. This bit is cleared after SpclCharInt is read. The BREAKInt interrupt can be routed to ISR[1] by enabling
SpclChrIntEn[4].
Bit 3: XOFF2Int
The XOFF2Int interrupt bit is set when an XOFF2 special character is received and special character detection is
enabled, through MODE2[4]. This interrupt is cleared upon reading SpclCharInt. The XOFF2Int interrupt can be routed
to the ISR[1] interrupt bit, if enabled through SpclChrIntEn[3].
Bit 2: XOFF1Int
The XOFF1Int interrupt bit is set when an XOFF1 special character is received and special character detection is
enabled, through MODE2[4]. This interrupt is cleared upon reading SpclCharInt. The XOFF1Int interrupt can be routed
to the ISR[1] interrupt bit, if enabled through SpclChrIntEn[2].
Bit 1: XON2Int
The XON2Int interrupt bit is set when an XON2 special character is received and special character detection is
enabled, through MODE2[4]. This interrupt is cleared upon reading SpclCharInt. The XON2Int interrupt can be routed
to the ISR[1] interrupt bit, if enabled through SpclChrIntEn[1].
Bit 0: XON1Int
The XON1Int interrupt bit is set when an XON1 special character is received and special character detection is
enabled, through MODE2[4]. This interrupt is cleared upon reading SpclCharInt. The XON1Int interrupt can be routed
to the ISR[1] interrupt bit, if enabled through SpclChrIntEn[0].
ADDRESS:
MODE:
RESET
NAME
BIT
______________________________________________________________________________________
—
7
0
0x06
COR
SPI/I
—
6
0
MultiDropInt
2
5
0
C UART with 128-Word FIFOs
BREAKInt
4
0
and Internal Oscillator
XOFF2Int
3
0
XOFF1Int
2
0
XON2Int
1
0
XON1Int
0
0
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