MAX3107ETG+ Maxim Integrated Products, MAX3107ETG+ Datasheet - Page 13

• Manufacturer Part Number: MAX3107ETG+
• Description: IC UART SPI/I2C 128 FIFO 24TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX3107ETG+

• Features: Internal Oscillators
• Number Of Channels: 4, QUART
• Fifo's: 128 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.35 V ~ 3.6 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• Mounting Type: Surface Mount
• Package / Case: 24-TQFN Exposed Pad
• Data Rate: 24 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 2.35 V
• Supply Current: 0.64 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• No. Of Channels: 1
• Uart Features: 128-Word Transmit / Receive FIFO, Half-Duplex Echo Suppression, Shutdown And Autosleep Modes
• Supply Voltage Range: 2.35V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TQFN-EP
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
—
7
8
9
PIN
SSOP
______________________________________________________________________________________
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
—
1
2
3
RTS/CLKOUT
DIN/A1
GPIO0
GPIO1
GPIO2
GPIO3
NAME
DGND
AGND
XOUT
V
CTS
RST
IRQ
XIN
RX
V
EP
SPI/I
V
TX
EXT
A
L
Serial-Data and Address 1 Input. When I2C/SPI is high, DIN/A1 functions as the DIN
SPI serial-data input. When I2C/SPI is low, DIN/A1 functions as the A1 I
address programming input and connects to DIN/A1 DGND or V
Active-Low Interrupt Open-Drain Output. IRQ is asserted when an interrupt is
pending.
Active-Low Reset Input. Drive RST low to force the UART into hardware reset mode.
In hardware reset mode, the oscillator and the internal PLL are shut down; there is
no clock activity.
Digital Interface Logic-Level Supply. V
RST, IRQ, DIN/A1, CS/A0, SCLK/SCL, DOUT/SDA, LDOEN, and I2C/SPI. Bypass V
with a 0.1FF ceramic capacitor to DGND.
Digital Ground
General-Purpose Input/Output 0. GPIO0 is user programmable as an input or output
(push-pull or open drain). GPIO0 has a weak pulldown resistor to ground.
General-Purpose Input/Output 1. GPIO1 is user programmable as an input or output
(push-pull or open drain). GPIO1 has a weak pulldown resistor to ground.
General-Purpose Input/Output 2. GPIO2 is user programmable as an input or output
(push-pull or open drain). GPIO2 has a weak pulldown resistor to ground.
General-Purpose Input/Output 3. GPIO3 is user programmable as an input or output
(push-pull or open drain). GPIO3 has a weak pulldown resistor to ground.
Active-Low Clear-to-Send Input. CTS is a flow-control input.
Active-Low Request-to-Send Output. RTS/CLKOUT can be set high or low by pro-
gramming bit 7 (RTS) of the LCR register.
Receive Input. Serial UART data input. RX has an internal weak pullup resistor to V
Transmit Output. Serial UART data output.
Transceiver Interface Level Supply. V
for RX, TX, RTS, CTS, and GPIO_. Bypass V
DGND.
Crystal Output. When using an external crystal, connect one end of the crystal to
XOUT and the other to XIN. When using an external clock source or the internal
oscillator, leave XOUT unconnected.
Crystal/Clock Input. When using an external crystal, connect one end of the crystal
to XIN and the other one to XOUT. When using an external clock source, drive XIN
with the external clock. When using the internal oscillator, leave XIN unconnected.
Analog Ground
Analog Supply. V
V
Exposed Paddle. Connect EP to AGND. EP is not intended as an electrical connec-
tion point. Only for TQFN-EP package.
A
2
with a 0.1FF ceramic capacitor to AGND.
C UART with 128-Word FIFOs
A
powers the internal oscillators, PLL, and internal LDO. Bypass
and Internal Oscillator
Pin Descriptions (continued)
FUNCTION
EXT
L
powers the internal logic-level translators for
powers the internal logic-level translators
EXT
with a 0.1FF ceramic capacitor to
L
.
2
C device
EXT
.
13
L