AD8436JCPZ-R7 Analog Devices Inc, AD8436JCPZ-R7 Datasheet - Page 14

• Manufacturer Part Number: AD8436JCPZ-R7
• Description: 65T4276
• Manufacturer: Analog Devices Inc

Specifications of AD8436JCPZ-R7

• Accuracy %: 0.5%
• Bandwidth: 1MHz
• Supply Current: 325µA
• Power Dissipation Pd: 18mW
• Supply Voltage Range: 4.8V To 36V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 20
• Operating Temperature Range: 0°C To +70°C

AD8436
Using the FET Input Buffer
The on-chip FET input buffer is an uncommitted FET input
op amp used for driving the 8 kΩ I-to-V input resistor of the
rms core. Pin 3, Pin 4, and Pin 5 are the I/O, Pin 6 is an optional
connection for gain in the input buffer, and and Pin 16 connects
power to the buffer (see Figure 3 and Table 4 for location and
description). Connecting Pin 16 to the positive rail is the only
power connection required because the negative rail is internally
connected. Because the input stage is a FET and the input
impedance must be very high to prevent loading of the source,
a large value (10 MΩ) resistor must be connected from midsupply
at Pin 11 (IGND) to Pin 5 (IBUFIN+) to prevent the input gate
from floating high.
For unity gain, connect Pin 3 (IBUFOUT) to Pin 4 (IBUFIN−).
For a gain of 2×, connect Pin 6 (IBUFGN) to ground. See Figure 8
and Figure 9 for large and small signal responses at the two
built-in gain options.
The offset voltage of the input buffer is ≤500 μV, depending on
grade. A capacitor connected between the Buffer Output Pin 3
(IBUFOUT) and Pin 2 (RMS) is recommended so that the input
buffer offset voltage does not contribute to the overall error.
Select the capacitor value for least minimum error at the lowest
operating frequency. Figure 32 is a schematic showing internal
components and pin connections.
Capacitor coupling at the input and output of the FET buffer is
recommended to avoid transferring the buffer offset voltage to
the output. Although the FET input impedance is extremely high,
the 10 MΩ centering resistor connected to IGND must be taken
into account when selecting an input capacitor value. This is simply
an impedance calculation using the lowest desired frequency,
and finding a capacitor value based on the least attenuation desired.
Because the 10 kΩ resistors are closely matched and trimmed to
a high tolerance, the input buffer gain can be increased to several
hundred with an external resistor connected to Pin 4 (IBUFIN−).
Figure 32. Connecting the FET Input Buffer
0.47µF
10µF
10MΩ
11
2
3
4
5
RMS
IBUFOUT
IBUFIN–
IBUFIN+
IGND
IBUFGN
IBUFV+
16
6
10kΩ
–
+
10kΩ
10pF
Rev. 0 | Page 14 of 20
The bandwidth diminishes at the typical rate of a decade per 20 dB
of gain, and the output voltage range is constrained. The small
signal response, as shown in Figure 8, serves as a guide. As an
example, suppose one wanted to detect small input signals at power
line frequencies? An external 10 Ω resistor connected from Pin 4 to
ground sets the gain to 101 and the 3 dB bandwidth to ~30 kHz,
which is more than adequate for amplifying power line frequencies.
Using the Output Buffer
The
for dc operation. Figure 33 shows a block diagram of the basic
amplifier and I/O pins. The amplifier is intended for noninverting
operation only; note that the 16 kΩ resistor, in series with the
inverting input of the amplifier, is used to balance the bias
current of the noninverting amplifier.
As with the input FET buffer, the amplifier positive supply is
pinned out separately for power sensitive applications. In normal
circumstances, the buffers are connected to the same supply as
the core. Figure 34 shows the signal connections to the output
buffer. Note that the input offset voltage contribution by the
bias currents are balanced by equal value series resistors,
resulting in near zero offset voltage.
For applications requiring ripple suppression in addition to the
single-pole output filter described previously, the output buffer
is configurable as a two-pole Sallen-Key filter using two external
resistors and two capacitors. At just over 100 kHz, the amplifier
has enough bandwidth to function as an active filter for low
frequencies such as power line ripple. For a modest savings in
cost and complexity, the external 16 kΩ feedback resistor can be
omitted, resulting in slightly higher V
CORE
Figure 35. Output Buffer Amplifier Configured as a Two-Pole, Sallen-Key
AD8436
CORE
OGND
OGND
8
OBUFIN+
16kΩ
OBUFIN–
OUT
output is a precision op amp that is optimized
Figure 34. Basic Output Buffer Connections
8
Figure 33. Output Buffer Block Diagram
16kΩ
OUT
9
9
16kΩ
2C
16kΩ
IBIAS
OUTPUT BUFFER
C
Low-Pass Filter
12
13
OBUFIN–
+
–
OBUFIN+
12
13
16kΩ
OBUFIN+
OBUFIN–
OS
16kΩ
(80 μV).
16kΩ
+
–
OBUFOUT
+
–
OBUFOUT
14
OBUFOUT
14