ISD5104SY Nuvoton Technology Corporation of America, ISD5104SY Datasheet - Page 74

• Manufacturer Part Number: ISD5104SY
• Description: IC VOICE REC/PLAY 2-4MN 28-SOIC
• Manufacturer: Nuvoton Technology Corporation of America
• Series: ISD5100r

Specifications of ISD5104SY

• Interface: I²C
• Filter Pass Band: 1.7 ~ 3.4kHz
• Duration: 2 ~ 4 Min
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• For Use With: ISD-ES511 - EVALUATION SYSTEM FOR ISD5100ISD-ES501 - EVALUATION SYSTEM FOR ISD5008
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Another common operation in the ISD5100 Series is the reading of digital data from the chip’s memory
array at a specific address. This requires the I
ISD5100 Series Slave device, and then receive data from the Slave in a single I
accomplish this, the data direction R/W bit must be changed in the middle of the command. The
following example shows the Master sending the Slave address, then sending a Command Byte and 2
bytes of address data to the ISD5100-Series, and then immediately changing the data direction and
reading some number of bytes from the chip’s digital array. An unlimited number of bytes can be read
in this operation. The “N” not-acknowledge cycle from the Master forces the end of the data transfer
from the Slave. The following example details the transfer explained in
datasheet.
Master Reads from the Slave after setting data address in Slave (Write data address, READ Data)
Start Bit
Master
From
S
Start Bit
Start Bit
Master
Master
From
From
SLAVE ADDRESS
S
S
From Master
SLAVE ADDRESS
Master Reads from Slave immediately after first byte (Read Mode)
SLAVE ADDRESS
From Master
acknowledgement
Master
acknowledgement
From
acknowledgement
R/W
Master
From
R/W
Master
from slave
R
From
W A
R/W
from slave
from slave
R A
A
COMMAND BYTE
8 BITS of DATA
STATUS W ORD
From Slave
From Slave
acknowledgement
acknowledgement
acknowledgement
from slave
from Master
A
from Master
A
- 74 -
2
A
C interface Master to first send an address to the
High ADDR. BYTE
8 BITS of DATA
From Slave
High ADDR. BYTE
From Slave
acknowledgement
acknowledgement
from Master
from slave
A
A
acknowledgement
Publication Release Date: Oct 31, 2008
from Master
Low ADDR. BYTE
A
section 7.5.4
ISD5100 SERIES
8 BITS of DATA
acknowledgement
From Slave
Low ADDR BYTE
from slave
From Slave
not-acknowled
from Master
not-acknowledged
A
from Master
on page 47 of this
2
C operation. To
N
Stop Bit
Master
From
P
Revision 1.42
N
Stop Bit
Master
From
P