LTC2632ACTS8-HZ12#PBF Linear Technology, LTC2632ACTS8-HZ12#PBF Datasheet - Page 20

• Manufacturer Part Number: LTC2632ACTS8-HZ12#PBF
• Description: 48T3784
• Manufacturer: Linear Technology

Specifications of LTC2632ACTS8-HZ12#PBF

• Resolution (bits): 12bit
• Input Channel Type: Serial
• Data Interface: 3-Wire, Serial
• Supply Voltage Range - Analog: 4.5V To 5.5V
• Supply Current: 500µA
• Digital Ic Case Style: TSOT-23
• No. Of Pins: 8
• Rohs Compliant: Yes

LTC2632
OPERATION
Voltage Output
The LTC2632’s integrated rail-to-rail amplifier has guar-
anteed load regulation when sourcing or sinking up to
10mA at 5V, and 5mA at 3V.
Load regulation is a measure of the amplifier’s ability to
maintain the rated voltage accuracy over a wide range of
load current. The measured change in output voltage per
change in forced load current is expressed in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to ohms. The amplifier’s DC output
impedance is 0.1Ω when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 50Ω typical channel resistance of the output devices
(e.g., when sinking 1mA, the minimum output voltage is
50Ω • 1mA, or 50mV). See the graph Headroom at Rails
vs Output Current in the Typical Performance Charac-
teristics section.
The amplifier is stable driving capacitive loads of up to
500pF .
Rail-to-Rail Output Considerations
In any rail-to-rail voltage output device, the output is lim-
ited to voltages within the supply range.
Since the analog output of the DAC cannot go below ground,
it may limit for the lowest codes as shown in Figure 4b.
Similarly, limiting can occur near full-scale when the REF
pin is tied to V
(FSE) is positive, the output for the highest codes limits
at V
occur if V
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
20
CC
, as shown in Figure 4c. No full-scale limiting can
REF
is less than V
CC
. If V
REF
= V
CC
CC
–FSE.
and the DAC full-scale error
Board Layout
The PC board should have separate areas for the analog and
digital sections of the circuit. A single, solid ground plane
should be used, with analog and digital signals carefully
routed over separate areas of the plane. This keeps digital
signals away from sensitive analog signals and minimizes
the interaction between digital ground currents and the
analog section of the ground plane. The resistance from
the LTC2632 GND pin to the ground plane should be as
low as possible. Resistance here will add directly to the
effective DC output impedance of the device (typically
0.1Ω). Note that the LTC2632 is no more susceptible to
this effect than any other parts of this type; on the con-
trary, it allows layout-based performance improvements
to shine rather than limiting attainable performance with
excessive internal resistance.
Another technique for minimizing errors is to use a sepa-
rate power ground return trace on another board layer.
The trace should run between the point where the power
supply is connected to the board and the DAC ground pin.
Thus the DAC ground pin becomes the common point for
analog ground, digital ground, and power ground. When
the LTC2632 is sinking large currents, this current flows
out the ground pin and directly to the power ground trace
without affecting the analog ground plane voltage.
It is sometimes necessary to interrupt the ground plane
to confine digital ground currents to the digital portion of
the plane. When doing this, make the gap in the plane only
as long as it needs to be to serve its purpose and ensure
that no traces cross over the gap.
Bypass capacitors should be placed as close to the pins
as possible with a low impedance path to GND.
2632fa